High frequency transistor layout for low source drain...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S341000, C257S342000, C257SE29120

Reexamination Certificate

active

07928517

ABSTRACT:
An RF field effect transistor has a gate electrode, and comb shaped drain and source electrodes, fingers of the comb shaped drain being arranged to be interleaved with fingers of the source electrode, the source and drain electrodes having multiple layers (110,120,130,140). An amount of the interleaving is different in each layer, to enable optimization, particularly for low parasitic capacitance without losing all the advantage of low current density provided by the multiple layers. The interleaving is reduced for layers further from the gate electrode by having shorter fingers. The reduction in interleaving can be optimized for minimum capacitance, by a steeper reduction in interleaving, or for minimum lateral current densities in source and drain fingers, by a more gradual reduction in interleaving. This can enable operation at higher temperatures or at higher input bias currents, while still meeting the requirements of electro-migration rules.

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Tiemeijer, L.F et al. A Record Hight 150 GHz Fmas Realized at 0.18um Gate Length in an Industrial RF-CMOS Technology. Philips Research Laboratories. Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands.

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