High frequency signal isolation in a semiconductor device

Details High frequency signal isolation in a semiconductor device High frequency signal isolation in a semiconductor device

2001-11-02

2003-05-13

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S127000, C257S544000, C257S549000, C257S546000, C257S550000, C257S509000, C257S547000, C257S275000

Reexamination Certificate

active

06563181

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices, and more particularly, to high frequency signal isolation in a semiconductor device.
BACKGROUND OF THE INVENTION
To reduce cost in integrated circuit design, it is desirable to include as much functionality as possible on a single integrated circuit. For example, in a low cost wireless communication system, it is desirable to include the RF (radio frequency) circuits on the same integrated circuit as the digital logic circuits. However, noise generated by the digital logic circuits can be injected into sensitive RF circuit blocks such as phase locked loops (PLL) and low noise amplifier circuits. Conceptually, an ideal Faraday cage prohibits external electromagnetic interference and provides perfect signal isolation. In an integrated circuit, implanted wells are used to reduce the effect of noise and to provide signal isolation. In a CMOS twin well process with a p-type substrate, the pn junction between n-well and p-type substrate provides some signal isolation for PMOS. The NMOS signal isolation is accomplished using a deep n+ implant (DNW) with an n-well to create an isolated p-well (IPW) pocket, and is sometimes referred to as a triple well process. Implanted wells as used to approximate a Faraday cage in integrated circuits, reduce the effect of noise. However, the use of implanted wells fails to provide adequate signal isolation at higher RF frequencies.
FIG. 1
illustrates a top view of a prior art semiconductor device
10
.
FIG. 2
illustrates a cross-sectional view of the prior art semiconductor device
10
of FIG.
1
. Semiconductor device
10
has a p substrate
18
. A deep n-well implant
16
together with a n-well ring
15
creates an-isolated p-well pocket
12
. A plurality of p+ well ties
14
is implanted in the surface of the isolated p-well
12
. Electronic circuits are built into the surface of the isolated p-well (not shown). The isolated p-well
12
functions to isolate the circuits implemented in the well from circuits that are implemented outside of the well. However, the deep n-well implant
16
has a relatively high resistance that is undesirable for signal isolation in the RF frequency range.


REFERENCES:
patent: 6349067 (2002-02-01), Hsu et al.
Wu, “A High Aspect-Ratio Silicon Substrate-Via Technology and Applications: Through-Wafer Interconnects for Power and Ground and Faraday Cages for SOC Isolation,” IEEE, 4 pp. (2000).
Jordar, “A Simple Approach to Modeling Cross-Talk in Integrated Circuits,” IEEE Journal of Solid-State Circuits, vol. 29, No. 10, Oct. 1994, pp. 1212-1219.
Hamel, Substrate Crosstalk Suppression Capability of Silicon-on-Insulator Substrates with Buried Ground Planes (GPSOI), IEEE Microwave and Guided Wave Letters, vol. 10, No. 4, Apr. 2000, pp. 134-135.

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