High frequency pipeline decoupling queue with non-overlapping re

Details High frequency pipeline decoupling queue with non-overlapping re High frequency pipeline decoupling queue with non-overlapping re

1998-09-24

2000-08-29

Kim, Kenneth S.

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Reducing an impact of a stall or pipeline bubble

711110, 711167, G06F 1314

Patent

active

061122955

ABSTRACT:
A method and apparatus for expediting the processing of a plurality of instructions in a processor is disclosed. In one embodiment, said processor has a plurality of pipeline units to process a plurality of instructions. Each of said pipeline units has a plurality of pipe stages. Further, a decoupling queue is provided to decouple at least one of said pipe stages from another, wherein said decoupling generates non-overlapping read and write signals to support corresponding read and write operations within a single clock cycle of said processor.

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Weste, Neil H.E., and Eshraghian, Kamran. Principles of CMOS VLSI Design. A Systems Perspective; Second Edition. pp. 579-582 and pp. 651-654.

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