High-frequency phase locked loop circuit

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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331 2, 331 25, H03D 324

Patent

active

056756208

ABSTRACT:
A high-frequency phase locked loop circuit effectively increases the maximum frequency associated with the CMOS technology. The circuit includes a first phase-locked loop sub-circuit having an input and an output, a second phase-locked loop sub-circuit having an input coupled to the input of the first phase-locked loop circuit and an output, and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop sub-circuits and an output. The first and second phase-locked loop may be arranged in parallel or in a master/slave relationship.

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