Electronic digital logic circuitry – Signal sensitivity or transmission integrity
Reexamination Certificate
2001-11-09
2003-04-08
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
C326S083000, C327S382000
Reexamination Certificate
active
06545502
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to high frequency differential amplifiers and more particularly to high frequency MOS differential amplifiers having high transconductance, matched differential devices, and minimal DC offset at the output.
2. Description of the Related Art
While designing high frequency amplifiers in MOS technology, designers are often forced to use small or even the minimum channel length of the technology for the amplifier transistors. This is needed to meet the high transconductance required by the application. However, if the amplifier is differential, serious problems can be encountered. While using small channel lengths, the matching of the differential devices is poor due to etching inaccuracies in the channel length. This results in DC offsets, low common mode rejection ratio (CMRR) and poor differential performance. For variable gain amplifiers based on the Gilbert Cell, the mismatches can lead to a lot of spread in the variable gain characteristics. The nicely balanced performance of the Gilbert Cell is also affected.
FIGS. 1 and 3
show a high frequency fixed and a Gilbert Cell based variable gain amplifier, respectively, having inputs In
1
, In
2
and outputs Out
1
, Out
2
. A power source V
DD
connects via two load resistors
11
and
12
(R
L
) to the drain of M
1
, M
2
and M
3
, M
4
. A series resistance
21
,
22
,
21
′,
22
′ (R
S
) couples each transistor via a current source
51
,
52
(IS), with current I
0
(for FIG.
3
: I
0
+&Dgr;, I
0
−&Dgr;I
0
), to ground. The current splits unequally between the differential transistors M
1
, M
2
and M
3
, M
4
if there are small differences in their channel lengths. This results in widely different transconductances between them and as a consequence the CMRR and differential and other balanced characteristics are spoilt. The unequal currents also cause DC offset at the amplifier outputs. As a result, the output signal handling capability is reduced.
FIGS. 2 and 4
a,
4
b
show how multiple stages of such amplifier stages have to be connected. Capacitive coupling
91
,
92
,
91
′,
92
′,
91
″,
92
″, (C
C
) between stages and at the input is used to prevent propagation and further amplification of DC offset appearing at the outputs of every amplifying stage. However, parasitic capacitances
71
,
72
,
71
′,
72
″,
71
″,
72
″, (C
P
) on the bottom plate of the coupling capacitors C
C
load the outputs of the amplifier stages and this adversely affects the high frequency response of the overall amplifier. In addition, gate resistors
81
,
82
,
81
′,
82
′ (R
G
)are coupled between a second power supply V
GG
and the inputs of each amplifier stage.
Transistors M
1
, M
3
and M
2
, M
4
of
FIG. 4
a
are coupled via load resistors
11
,
12
(R
L
), respectively, to power supply V
DD
. Transistors M
5
, M
7
and M
6
, M
8
of
FIG. 4
b
are coupled via load resistors
11
′,
12
′ (R
L
), respectively, to power supply V
DD
.
Note that throughout this document the same numerals and characters designate the same component.
Since usage of minimum channel length devices cannot be ruled out for high frequency applications, a topology modification to the conventional differential amplifier structures is needed to minimize the above problems.
Related art referring to differential amplifiers and Gilbert Cells are: U.S. Pat. No. 5,880,631 (Sahota), U.S. Pat. No. 5,949,286 (Jones), U.S. Pat. No. 6,111,463 (Kimura), and U.S. Pat. No. 6,229,395 (Kay) all use a single current source for a differential transistor pair with the disadvantages discussed above.
It should be noted that none of the above-cited examples of the related art connect each differential transistor only to a current source and from there to a reference voltage nor do they insure that the bias current for each differential transistor is exactly I
0
/2 of the transistor pair.
SUMMARY OF THE INVENTION
It is an object of at least one embodiment of the present invention to provide high frequency differential amplifier circuits and methods which utilize amplifier transistors using a small or minimum channel lengths of the technology.
It is another object of the present invention to provide high transconductance for those amplifier transistors.
It is yet another object of the present invention to provide excellent matching of the transconductance of the differential amplifier transistors.
It is still another object of the present invention to provide circuits and methods which are not sensitive to DC offsets at the inputs to those differential amplifiers.
It is a further object of the present invention to provide circuits and methods which do not cause DC offsets at the outputs of the differential amplifier.
It is yet a further object of the present invention to maintain good common mode rejection ratio (CMRR) at the signal frequencies of interest.
It is still a further object of the present invention to provide AC differential gains equal to those of the prior art.
It is lastly an object of the present invention to reduce the spread in the gain control characteristics for variable gain amplifiers.
These and many other objects have been achieved by a circuit topology which ensures that bias currents of the differential transistors are exactly equal, i.e., each differential transistor carries half of the total current I
0
of the differential amplifier. That is, the current in each differential transistor is I
0
/2. To insure a good match between the current sources, the current source devices are made with long channel lengths. This causes the DC bias conditions to be perfectly determined and the circuits are not sensitive to DC offsets at the outputs. Another benefit is that the transconductance of the differential devices is nearly equal. Any small differences are due to slightly different aspect ratios. The spread in the gain control characteristics for the variable gain differential amplifier can also be further reduced by making the aspect ratio of the first transistor pair larger than that of the second transistor pair. To insure good AC gain, impedances are coupled between the junctions of each differential transistor pair and its current source.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.
In the following, first and second conductivity types are opposite conductivity types, such as N and P types. Each embodiment includes its complement as well.
REFERENCES:
patent: 4710728 (1987-12-01), Davis
patent: 5420524 (1995-05-01), Webster
patent: 5880631 (1999-03-01), Sahota
patent: 5949286 (1999-09-01), Jones
patent: 6084469 (2000-07-01), Lorenz
patent: 6111463 (2000-08-01), Kimura
patent: 6229955 (2001-05-01), Kay
Dasgupta Uday
Yeoh Wooi Gan
Ackerman Stephen B.
Chang Daniel D.
Institute of Microelectronics
Saile George O.
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