Static information storage and retrieval – Interconnection arrangements
Patent
1998-09-17
2000-08-15
Dinh, Son T.
Static information storage and retrieval
Interconnection arrangements
365 52, G11C 506
Patent
active
061046299
ABSTRACT:
Memory chips (15) are mounted perpendicularly on a memory module substrate (14) to achieve a close spacing between the chips. A plurality of memory chip signal lines (20) are located on the memory module substrate (14) and the memory chips (15) are electrically coupled to the memory chip signal lines at spaced apart chip coupling points (23). Digital signals are driven to the memory chip signal lines (20) through signal lines (21) having a first level impedance. The memory chip signal lines (20) have a second level impedance greater that the first level impedance. The spacing between the chip coupling points (23) is chosen such that the effective impedance level of the memory chip signal lines (20) substantially matches the lower, first level impedance.
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patent: 5260892 (1993-11-01), Testa
patent: 5319591 (1994-06-01), Takeda et al.
patent: 5397747 (1995-03-01), Angiulli et al.
patent: 5831890 (1998-11-01), Selna et al.
Henle, "Verticle Chip Packagin", IBM Technical Disclosure Bulletin, vol. 20, No. 11A, Apr. 1978.
Culbertson Russell D.
Dinh Son T.
England Anthony V. S.
International Business Machines - Corporation
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