High-frequency, high-signal-density, surface-mount...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

11287951

ABSTRACT:
Methods for designing SMT connector footprints are disclosed. A circuit board may have disposed thereon an arrangement of SMT pads and corresponding vias. The arrangement of vias may differ from the arrangement of SMT pads. The arrangement of SMT pads may differ from the arrangement of contacts in a connector the footprint is designed to receive. The terminal ends of the contacts may be jogged or bent for electrical connection with the SMT pads. The SMT pads and vias may be arranged in a number of ways that increase signal contact density of the board, while limiting cross-talk and providing adequate impedance and routing space on the board. An interactive tool for designing such a footprint is disclosed.

REFERENCES:
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patent: 5516030 (1996-05-01), Denton
patent: 6150729 (2000-11-01), Ghahghahi et al.
patent: 6198635 (2001-03-01), Shenoy et al.
patent: 6232564 (2001-05-01), Arndt et al.
patent: 6538213 (2003-03-01), Carden et al.
patent: 6717825 (2004-04-01), Volstorf
patent: 2004/0216071 (2004-10-01), Miller
patent: 2007/0050736 (2007-03-01), Bickford et al.
patent: WO 2005/081595 (2005-09-01), None
patent: WO 2005/081596 (2005-09-01), None
patent: WO 2006/053891 (2006-05-01), None
De Geest, J. PhD. et al., “Connector Footprint Optimization Enables 10Gb+ Signal Transmission”, DesignCon 2005, 1-25.

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