Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2000-02-18
2001-07-24
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S120000, C710S108000, C326S030000, C326S086000, C326S093000
Reexamination Certificate
active
06266730
ABSTRACT:
BACKGROUND OF THE INVENTION
As computer processors increase in speed they require increased information bandwidth from other subsystems supporting the processor. An example is the large amount of bandwidth needed by video and 3D image processing from a computer memory subsystem. Another example is a main memory subsystem. One or more high frequency buses are typically employed to provide the bandwidth required. The higher the frequency of operation of the bus, the greater the requirement that the signals on the bus have high-fidelity and equal propagation times to the devices making up the subsystem. High-fidelity signals are signals having little or no ringing and controlled and steady rising and falling edge rates. Many obstacles are encountered in assuring the uniform arrival times of high-fidelity signals to devices on the bus. One such obstacle is a requirement that a subsystem be modular, meaning that portions of a subsystem may be added and possibly removed. The modularity requirement implies that devices that are part of the modular subsystem be mounted on a separate substrate or module which couples to another board, the motherboard. It also implies the use of connectors if both addition and removal is required. Other obstacles are the number of layers of the motherboard on which routing of the bus is allowed and whether the bus is routed in a straight line or routed with turns. Too few layers on a motherboard, or a module, and turns of the lines may not permit the construction of the bus lines in a way necessary to achieve uniform arrival times of high-fidelity signals to devices on the bus.
Modular subsystems in computers have numerous advantages, some of which are field upgradability, replacement of a failing device, flexibility of initial configuration, and increased device density. Currently, so called SIMMs (single in-line memory module) and DIMMs (dual in-line memory modules) are examples of computer memory systems employing such modules. Because of these advantages and the desirability of having high performance modular memory subsystems, it is especially important to have buses with uniform arrival times to devices in applications where modules are employed.
One form of module technology, using buses, is oriented to a grid topology having three groups of lines as shown in FIG.
1
. In the first group
120
, all of the lines connect to all devices on all modules
140
a-c.
In the second group
110
, the group is partitioned into a number of subgroups,
112
,
114
,
116
, and
118
, which connect to a corresponding device in each module. For example, in
FIG. 1
, a portion, say 1, 4, or 8 lines are routed to a similarly situated device in each module. In the third group
130
, the lines are typically radially connected to the modules and all devices in a particular module connect to the dedicated radial line or lines. For a memory module, the first group
120
is representative of address bus and clock lines, the second group
110
of the data bus or buses and the third group
130
of the control lines, such as RAS and CAS. Corresponding to each group is a representative transmission line having a certain set of characteristics, such as propagation delay and loaded or unloaded characteristic impedance, which are different for each group. This leads to difficulty in matching the arrival of signals of each group at the devices on the modules and limits the performance that can be obtained from such a topology due to waiting on the delays of the slowest group of lines, which waiting also includes the settling of the lines when not properly terminated.
A circuit model of a tapped line, typical of the second group of lines, is shown in FIG.
3
. As shown, in this topology, each line in a group is typically connected to a module by means of a stub
360
which acts as tap off of the line as shown in FIG.
2
and
FIG. 3. A
stub is defined as a length of line tapped from a transmission line and having a round trip delay which is greater than the rise time (or fall time) of the signal. Since the stub
360
(
160
in
FIG. 2
) typically has a different impedance than the line being tapped, it is often necessary to insert a resistor
320
, as shown in
FIG. 3
, in series with the stub to mitigate the effect of reflections at the connection point of the stub to the line. If the line impedance is about 50 ohms and the impedance of the stub is about 75 ohms, a resistor of approximately 20-25 ohms is typically chosen usually by trial and error for the best results under certain conditions. This resistor has the possibly undesirable effect of attenuating the voltage swing of the signal as the signal passes through the resistor, requiring a driver on the stub to have a proportionately larger voltage swing. Another undesirable effect is the RC delay due to the added series resistor and the device capacitance. The resistors and stubs also lead to low-fidelity signals at the devices. Also, as shown in
FIG. 3
, the line is terminated by resistors
350
at both ends to minimize reflections from the ends of the line. This requires that the drivers on the line supply twice as much steady state current as compared to a line terminated at only one end.
As mentioned above, the need to incorporate memory modules into the design of the modular system may also imply the use of connectors. In general, connectors have undesirable characteristics for operating at high frequency, such as inductance, capacitance, or crosstalk which introduces noise from one line into another line. Failure to take the connector characteristics into account leads to non-uniform arrival characteristics and low-fidelity signals when crossing a connector boundary resulting in lower performance (due to longer settling times, reduced noise margin or different signal propagation speed) from the modular system using the lines.
The physical shape, size and construction of the memory module is important to consider as well. The physical nature of the memory module may force the IC devices mounted on the module to be arranged in a less-than-optimal topology for the high frequency transmission line layout. High frequency signaling typically requires that electrical paths be controlled; signal delays need to be minimized or matched and impedance needs to be tightly controlled for high frequency operation, where high frequency means frequencies in the range of 200 megaHertz to at least 1,000 megahertz.
For the foregoing reasons, there is a need for a bus connecting to a plurality of devices which has uniform arrival times of high-fidelity signals to the devices on the bus, even when modules and connectors are employed to build a computer subsystem in which the bus is used and despite the physical size, shape and construction of the module and the number of devices mounted on it.
SUMMARY OF THE INVENTION
The present invention is directed to a high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially
Crisp Richard DeWitt
Garrett, Jr. Billy Wayne
Gasbarro James A.
Liaw Haw-Jyh
Nguyen David
Dharia Rupal
Pennie & Edmonds LLP
Rambus Inc.
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