Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-06-28
2002-04-23
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S592000, C438S275000, C438S638000
Reexamination Certificate
active
06376351
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of a gate with a wide top and more particularly to the fabrication of a gate with a wide top in a chip with both digital and RF circuits.
2) Description of the Prior Art
As semiconductor technologies continue to require improvements in the performance of integrated circuit devices, processes must be developed to meet those requirements which easily integrate into existing fabrication processes. In particular, increases in speed require low sheet resistance gates to minimize time constants, as well as narrower gate widths, thinner gate dielectrics and shallower source and drain regions. More particularly, the inventors have found that FET's used in RF circuits require even low gate sheet resistance because this can increase Fmax and reduce noise.
As the gate length get smaller, Fmax degrades due to larger parasitics. FMax is the frequency where the maximum power gain of the transistor degrades to unity. Parasitics are the gate resistance, gate to source capacitance, gate to drain capacitance and other junction capacitances. The paracitics are increasing because the gate are getting narrower thus increasing Rg; and the LDD I/I doses are increasing thereby increasing the capacitance.
There are processes that form wide top gates. However there is a need to improve these processes.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 6,063,675 (Rodder) shows a gate with a wide T top.
U.S. Pat. No. 5,731,239 (Wong et al.) teaches a silicide process for a gate top.
U.S. Pat. No. 5,650,342 (Satoh et al.) shows a T-shaped gate with a wide top.
U.S. Pat. No. 6,010,954 (Ho et al.) shows a T-shaped gate with a wide top.
U.S. Pat. No. 6,069,047 (Wanlass) and U.S. Pat. No. 5,970,375 (Gardner et al.) show gate contact processes.
U.S. Pat. No. 5,268,330 (Givins et al.) shows a process to improve the gate sheet resistance.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a gate stack with a wide top.
It is an object of the present invention to provide a method for fabricating a gate stack with a wide top that has a W/TiN/CoSix interface that reduces gate resistance.
It is an object of the present invention to provide a method for fabricating a gate stack with a wide top that is self aligned between the metal and poly gate.
It is an object of the present invention to provide a method for fabricating a chip with both digital/base band and RF circuits where in the RF circuit area, the gate stack has a wide top.
To accomplish the above objectives, the present invention provides a method a chip with both digital and RF circuits where in the a RF circuit, the gate stack has a wide top.
A substrate has a digital area and a rf area. Devices used in digital circuits will be formed in the digital area and devices used in RF circuits will be formed in the RF area.
The following steps are performed in both the digital area and the rf area, unless otherwise stated. We form a gate dielectric and a gate electrode over a substrate. Next, we form LDD regions adjacent to the gate electrode. Then, we form spacers on the sidewall of the gate dielectric and the gate electrode. Source and drain (S/D) regions are formed aside the gate electrode. Next, we form source and drain silicide regions over the S/D regions and gate silicide regions over the gate electrode.
We form a stop layer over the substrate, the source and drain silicide regions, the gate silicide regions, and the spacers. Then, we form a first interlevel dielectric (ILD) layer over the stop layer. We polish the first interlevel dielectric layer using the stop layer and the gate silicide region as a polish stop. In the same polish step, we polish the stop layer using the gate silicide region as a polish stop to expose the gate silicide region. Subsequently, we form a polish stop layer on the first interlevel dielectric (ILD) layer. A second interlevel dielectric layer is formed over the polish stop layer.
In the digital area, we form a contact holes through the first and the second interlevel dielectric layers to expose the gate silicide region and the source and drain silicide regions. In the same process step, in the rf area, we form a contact trench through the second interlevel dielectric layer, the polish stop layer, and the first interlevel dielectric layer, and the stop layer to expose the source and drain silicide regions.
In the rf area, a wide gate trench top opening is formed through the second interlevel dielectric layer and the polish stop layer exposing gate silicide region.
In the digital area, conductive material is deposited to fill the contact holes to form contact plugs and to the silicide gate region and the silicide source/drain regions. In the same step, in the RF area we deposit conductive material filling the wide gate trench top opening to form a wide gate top and filling the contact trench to form a contact plug contacting the source and drain (S/D) silicide regions.
We form a first metal layer over the second interlevel dielectric layer. The first metal layer contacting the contact plugs and the wide gate top.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 5268330 (1993-12-01), Givens et al.
patent: 5650342 (1997-07-01), Satoh et al.
patent: 5731239 (1998-03-01), Wong et al.
patent: 5970375 (1999-10-01), Gardner et al.
patent: 5976972 (1999-11-01), Inohara et al.
patent: 6010954 (2000-01-01), Ho et al.
patent: 6063675 (2000-05-01), Rodder
patent: 6069047 (2000-05-01), Wanlass
patent: 6121129 (2000-09-01), Greco et al.
patent: 6180501 (2001-01-01), Pey et al.
patent: 6284613 (2001-09-01), Subrahmanyam et al.
patent: 6326291 (2001-12-01), Yu
patent: 2001/0001075 (2001-05-01), Ngo et al.
Ackerman Stephen B.
Niebling John F.
Roman Angel
Saile George O.
Stoffel William J.
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