High-fanin static multiplexer

Details High-fanin static multiplexer High-fanin static multiplexer

2006-10-31

2006-10-31

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

C327S409000, C327S410000

Reexamination Certificate

active

07129755

ABSTRACT:
An improved high-fanin multiplexer that is highly-scalable, fast and area-efficient. In one embodiment of the present invention, multiple logic “legs” are attached to a common output line. Each leg comprises one pMOS pull-up transistor and one nMOS pull-down transistor. The gate of the pMOS transistor in each leg is connected to the output of an And-Or-Invert (AOI) gate whose inputs are connected to a plurality of select lines and a plurality of data lines. The gate of the nMOS transistor in each leg is connected to the output of an Or-And-Invert (OAI) gate whose inputs are connected to a plurality of select lines (the logical complements of the select lines for the AOI), and a plurality of data input lines. The high-fanin multiplexer of the present invention offers numerous advantages over the prior art. In particular, the high-fanin multiplexer of the present invention has very small self-loading allowing a large number of inputs while also maintaining a high fan out speed. In addition, the small input capacitive load allows the driving gates to be small, thereby conversing surface area within an integrated circuit.

REFERENCES:
patent: 5543731 (1996-08-01), Sigal et al.
patent: 5773995 (1998-06-01), Crocker
patent: 6124736 (2000-09-01), Yamashita et al.
Horenstein, “Microelectric Circuits & Devices”, no month, 1990, Prentice-Hall, Inc., pp. 753-755.

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