High f MAX deep submicron MOSFET

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S383000, C257S384000, C257S412000, C257S411000, C257S413000

Reexamination Certificate

active

07061056

ABSTRACT:
A method of forming a high fMAXdeep submicron MOSFET, comprising the following steps of. A substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A first ILD layer is formed over the substrate and the MOSFET. The first ILD layer is planarized to expose the silicide portion over the gate electrode. A metal gate portion is formed over the planarized first ILD layer and over the silicide portion over the gate electrode. The metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode. A second ILD layer is formed over the metal gate portion and the first ILD layer. A first metal contact is formed through the second ILD layer contacting the metal gate portion, and a second metal contact is formed through the second and first ILD layers contacting the drain completing the formation of the high fMAXdeep submicron MOSFET. Whereby the width of the metal gate portion reduces Rgand increases the fMAXof the high fMAXdeep submicron MOSFET.

REFERENCES:
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patent: 6376351 (2002-04-01), Tsai

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