High energy buried layer implant to provide a low resistance p-w

Details High energy buried layer implant to provide a low resistance p-w High energy buried layer implant to provide a low resistance p-w

1994-07-01

1996-07-30

Nguyen, Viet Q.

Static information storage and retrieval

Systems using particular element

Semiconductive

365182, 365174, 257382, 257377, 257400, H01L 2706, H01L 2972

Patent

active

055418759

ABSTRACT:
A buried layer which is highly doped and implanted with high energy in a lightly doped isolated well in which an array of flash EPROM cells are provided. The buried layer is doped with the same conductivity dopant as the well in which it is provided, for example a p.sup.+ -type buried implant is provided in a p-type well. The buried layer enables channel size of the flash EPROM cells to be reduced providing a higher array density. Channels of the flash EPROM cells are reduced because the buried layer provides a low resistance path between channels of the flash EPROM cells enabling erase to be performed by applying a voltage potential difference between the gate and substrate of a cell.

REFERENCES:
patent: 4429326 (1984-01-01), Watanabe et al.

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