Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Amorphous semiconductor
Reexamination Certificate
2000-03-09
2001-05-01
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Amorphous semiconductor
C438S162000, C438S167000, C438S172000, C438S486000
Reexamination Certificate
active
06225196
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an integrated circuit constituted of semiconductor devices for operation and storage which are widely utilized in electronic devices such as a computer and communication devices. More particularly, the invention relates to a high electron mobility transistor (HEMT) using two-dimensional electron gas or two-dimensional hole gas as carriers.
2. Description of the Related Art
There are many methods of enhancing mobility of carriers in a semiconductor device. As one of such methods, there has been suggested HEMT in Japanese Journal of Applied Physics, Vol. 225, No. 19, 1980. The suggested HEMT is made of compound semiconductor such as GaAs, and utilizes a quantum well or potential well as a channel of a transistor. Such a quantum or potential well is formed by band off-set caused by joining two semiconductors having different electron affinity to each other. With regard to silicon which is mainly used to make memory and logic transistors thereof, there has been suggested HEMT made of Si/SiGe family utilizing a difference in electron affinity therebetween (Applied Physics Letters, Vol. 45, No. 11, 1984, pp. 1231-1233).
However, it is quite difficult to form qualified heterojunction because of a difference in lattice constant between Ge and Si. Thus, Japanese Unexamined Patent Publication No. 62-86867 has suggested HEMT made of silicon family, including a semiconductor layer
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made of crystal silicon, an amorphous SiC layer
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having smaller electron affinity than that of the crystal silicon layer
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, and a gate electrode
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formed on the amorphous SiC layer
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. The suggested HEMT utilizes an interface between the amorphous SiC layer
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and the crystal silicon layer
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to thereby accomplish higher mobility in a transistor.
However, the above mentioned conventional HEMT has problems as follows.
The first problem is that even if impurities were doped into the amorphous SiC layer as a carrier supply, it would be impossible to have a desired carrier concentration. This is because that since SiC is in amorphous condition and hence there are a lot of dangling bonds in the amorphous SiC layer
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, electrons or holes as carriers are trapped with such dangling bonds.
The second problem is that it is quite difficult to have a qualified interface between a crystal silicon layer and an amorphous SiC layer. The reason is as follows. When an amorphous SiC layer is made to grow by means of chemical vapor deposition (CVD) or molecular beam epitaxy (MBE), the amorphous SiC layer is influenced by an underlying silicon layer at an initial stage in growth, and thus grains tend to be formed at an interface between a crystal silicon layer and an amorphous SiC layer. Thus, the interface that is intended to be used as a channel becomes irregular, which does not ensure normal transistor operation.
The third problem is that there would be caused a risk of an increase in fabrication costs. The reason is that it would be necessary to prepare an apparatus for carrying out CVD used only for growth of SiC.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a field effect transistor and a method of fabricating the same both of which are capable of decreasing defects at an interface between an amorphous silicon layer and a crystal silicon layer, and increasing a concentration of carrier in a silicon substrate.
In one aspect, there is provided a field effect transistor including (a) a first semiconductor layer made of amorphous silicon hydride, and (b) a second semiconductor layer made of single crystal silicon having electron affinity greater than that of the amorphous silicon hydride, in which the first and second semiconductor layers cooperate with each other to form at a junction therebetween a potential well which forms a channel in which carriers transfer.
It is preferable that the first semiconductor layer is a layer containing impurities such as hydrogen doped therein. The potential well may form a channel for one of two-dimensional electron gas and two-dimensional source gas to transfer therethrough. It is preferable that the second semiconductor layer contains an epitaxial silicon layer made of intrinsic semiconductor.
There is further provided a field effect transistor including (a) an amorphous semiconductor layer made of amorphous silicon hydride containing impurities doped therein, (b) a semiconductor layer made of single crystal silicon having electron affinity greater than that of the amorphous silicon hydride, formed on the amorphous semiconductor layer, (c) a gate insulating film formed on the semiconductor layer, and (d) a gate electrode formed on the gate insulating film. The amorphous semiconductor layer and the semiconductor layer cooperate with each other to thereby form a potential well at a junction therebetween.
There is still further provided a field effect transistor including (a) a first semiconductor layer made of single crystal silicon, (b) a second semiconductor layer made of amorphous silicon hydride containing impurities doped therein and having electron affinity smaller than that of the single crystal silicon, (c) a gate insulating film formed on the second semiconductor layer, and (d) a gate electrode formed on the gate insulating film. The first and second semiconductor layers cooperate with each other to form a potential well at a junction therebetween.
There is yet further provided a field effect transistor including (a) a semiconductor substrate having a first electrical conductivity, (b) an amorphous semiconductor layer formed in the semiconductor substrate and made of amorphous silicon hydride in which impurities having a second electrical conductivity are doped, (c) source and drain regions formed on the amorphous semiconductor layer, the source and drain regions having a second electrical conductivity, (d) a semiconductor layer made of single crystal silicon and sandwiched between the source and drain regions on the amorphous semiconductor layer, the single crystal silicon having electron affinity greater than that of the amorphous silicon hydride, (e) a gate insulating film formed on the source and drain regions and the semiconductor layer, and (f) a gate electrode formed on the gate insulating film. The amorphous semiconductor layer and the semiconductor layer cooperate to each other to form a potential well at a junction therebetween which well contains carriers having a second electrical conductivity.
It is preferable for the semiconductor layer to have a first portion sandwiched between the source and drain regions on the amorphous semiconductor layer, and a second portion covering the first portion and the source and drain regions therewith, the gate insulating film being formed on the second portion. It is preferable that the second portion has higher purity than that of the first portion.
The above mentioned field effect transistor may further include a nitride film formed over the gate insulating film. The field effect transistor may further include an interlayer insulating film over the gate electrode and the gate insulating film, hydrogen contained in the interlayer insulating film being diffused into an amorphous semiconductor layer formed in the semiconductor substrate to thereby form the amorphous semiconductor layer made of amorphous silicon hydride in which impurities having a second electrical conductivity are doped. The field effect transistor may further include a second amorphous semiconductor layer formed below the amorphous semiconductor layer. The field effect transistor may further include an oxide layer formed below the amorphous semiconductor layer.
There is still yet further provided a field effect transistor including (a) a silicon substrate having a first electrical conductivity, (b) source and drain regions having a second electrical conductivity, formed in the silicon substrate, (c) a semiconductor layer made of single crystal silicon and sandwiched between the source and drain regions, (d) an amorphous semiconductor layer
Hayes, Soloway, Hennessey, Grossman & Hage
Malsawma Lex H.
NEC Corporation
Smith Matthew
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