High efficiency quasi-vertical DMOS in CMOS or BICMOS process

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257337, 257339, 257347, 257351, 257352, 257354, H01L 2976, H01L 2701

Patent

active

057773629

ABSTRACT:
A QVDMOS array 10 has QVDMOS devices with a silicide contact 42 to source 35 and body tie 36. The body tie 36 is enclosed by the source at the surface and extends beneath but not beyond the annular source 35. The QVDMOS is formed during a number of process steps that simultaneously form regions in NMOS, PMOS and bipolar devices.

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A. Watson Swager, "Power Ics weighing The Benefits Of Integration", EDN-Electrical Design News, vol. 39, No. 14, Newton, MA, Jul. 1994, pp. 68-72, 74, 76, 78, 80, 82.

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