Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1995-06-07
1998-07-07
Saadat, Mahshid D.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257337, 257339, 257347, 257351, 257352, 257354, H01L 2976, H01L 2701
Patent
active
057773629
ABSTRACT:
A QVDMOS array 10 has QVDMOS devices with a silicide contact 42 to source 35 and body tie 36. The body tie 36 is enclosed by the source at the surface and extends beneath but not beyond the annular source 35. The QVDMOS is formed during a number of process steps that simultaneously form regions in NMOS, PMOS and bipolar devices.
REFERENCES:
patent: H1435 (1995-05-01), Cherne et al.
patent: 4214359 (1980-07-01), Kahng
patent: 4313126 (1982-01-01), Krumm et al.
patent: 4554512 (1985-11-01), Aiello
patent: 4589004 (1986-05-01), Yasuda et al.
patent: 5191396 (1993-03-01), Lidow
patent: 5256893 (1993-10-01), Yasuoka
patent: 5317182 (1994-05-01), Zambrano et al.
patent: 5387875 (1995-02-01), Tateno
patent: 5430316 (1995-07-01), Contiero et al.
patent: 5432370 (1995-07-01), Kitamura et al.
patent: 5541429 (1996-07-01), Shibib
European Search Report mailed Sep. 12, 1996.
PCT Communication mailed Oct. 15, 1996.
A. Watson Swager, "Power Ics weighing The Benefits Of Integration", EDN-Electrical Design News, vol. 39, No. 14, Newton, MA, Jul. 1994, pp. 68-72, 74, 76, 78, 80, 82.
Harris Corporation
Martin Wallace Valencia
Saadat Mahshid D.
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