High efficiency power MOS switch

Details High efficiency power MOS switch High efficiency power MOS switch

1995-06-07

1997-11-18

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257342, 257343, H01L 2976, H01L 2994

Patent

active

056891296

ABSTRACT:
A power MOS switch (40) is an array of MOS devices that includes alternating drain columns and source columns. Each drain column includes a plurality of separate drain regions (300) that are closely spaced one from another, and each source column includes a continuous narrow elongated source distribution region (302) that extends the length of the column. A plurality of narrow source distribution branch regions (302) are connected to the elongated region and extend transversely from the elongated region at least partially between each separate drain region in each drain column adjacent to the source column. A gate region (303) separates the drain regions in each column from the adjacent source distribution regions.

REFERENCES:
patent: 4313126 (1982-01-01), Krumm et al.
patent: 4554512 (1985-11-01), Aiello
patent: 5136349 (1992-08-01), Yilmaz et al.
patent: 5256893 (1993-10-01), Yasuoka
patent: 5302845 (1994-04-01), Kumagai et al.
patent: 5355008 (1994-10-01), Moyer et al.
patent: 5387875 (1995-02-01), Tateno
A. Watson Swager, "Power ICs Weighing The Benefits Of Integration", EDN-Electrical Design News, vol. 39, No. 14, Newton, MA, Jul. 1994, pp. 68-72, 74, 76, 78, 80, 82.

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