Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2002-08-02
2004-11-02
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S115000
Reexamination Certificate
active
06812733
ABSTRACT:
FIELD OF INVENTION
The present invention relates to circuitry for drivers for digital outputs.
BACKGROUND TO THE INVENTION
The digital revolution has produced a need for analog circuitry that can be used for digital purposes, especially in the fields of telecommunications and networking.
Modern applications in the above fields require high efficiency driver circuitry that can drive both receiver and transmitter end terminations in a networked data communications link. Such an application requires an output voltage swing with a controllable amplitude along with high efficiency. Driver efficiency is dependent on the amount of drive current required to drive a given output voltage swing. Controllability is quantified by the ability to control dynamically the output voltage swing. Such controllability must also allow for the use of pre-emphasis and the use of variable output levels.
A number of solutions have been presented in the past that sought to provide the desired controllability and efficiency. Three architectures predominate in these solutions
a single differential pair (Class A output driver),
a class AB driver commonly used with LVDs (Low Voltage Differential Signalling) output drivers, and
a series terminated voltage mode driver.
The class A output driver consists of a CMOS current source I drive connected to a differential pair of transistors that are, in turn, connected to the output resistors. The resistors act as parallel termination to the transmission line. The differential pair switches the current between the resistors depending on whether a logic 1 or a logic 0 is required to be driven on the transmission line. A schematic diagram of a class A single differential pair output driver circuit is illustrated in FIG.
1
.
While the class A output driver is very simple and easy to implement, it is not very efficient. For 50 Ohm drivers (as in FIG.
1
), this driver requires that Idrive=4×Vswing/100 to generate a differential output voltage swing of Vswing. This value for Idrive is 4 times the ideal current drive. The output voltage swing is controllable by adjusting the amount of current (Idrive) in the tail of the differential pair. The voltage Vswing is also controllable by putting many of these types of drivers in parallel to generate a larger swing.
A second known architecture is discussed below, and utilizes a class AB driver illustrated in FIG.
2
. This circuit consists of two CMOS differential pairs of transistors. The top differential pair switches a PMOS current source and the bottom differential pair switches an NMOS current source. The outputs of these differential pairs are connected to a 100 Ohm differential termination resistor.
The circuit in
FIG. 2
requires that Idrive (2×Vswing)/100 to generate a differential output voltage swing of Vswing. The output voltage swing is controllable by adjusting the amount of current in the tail of the current sources of the differential pairs. The swing can also be controlled by placing multiple instances of this circuit in parallel. This circuit has a very controllable output swing but it is not very efficient.
A third known architecture is that illustrated in FIG.
3
. This circuit is a class AB voltage mode series terminated output driver implemented as a CMOS inverter drive with series termination. As can be seen, the circuit consists of two inverter circuits connected by a resistor divider circuit. An input signal and its complement are fed to the driver and, depending on the input, the inverters route current one way or the other. The inverters will always act in opposite directions and the direction of the current through the middle resistor in the resistor divider circuit determines whether the output is a logic 1 or a logic 0.
This third architecture, if designed properly, only requires that Idrive=Vswing/100 to drive an output voltage of Vswing. Unfortunately, the output swing is not adjustable and is completely dependent on the ratio of the resistor divider and the supply voltage level. Since the supply level and the resistor divider ratio are not easily dynamically controllable, the output voltage swing is not easily dynamically controllable.
From the above, the issues with the three architectures are clear—the single differential pair architecture and the class AB driver (
FIGS. 1 and 2
) both have controllable output voltage swing levels but are not very efficient. While the voltage mode driver has the desired efficiency, it does not have an easily controllable output voltage swing. What is therefore required is a driver that has the controllability of the first two designs and the efficiencies of the voltage mode driver.
SUMMARY OF THE INVENTION
The present invention provides circuits and devices for an efficient, controllable output driver. The output driver circuit includes a series terminated voltage mode driver circuit in parallel with a current mode driver circuit. This output driver allows for a highly efficient driver but with an easily controllable output. It can be used for driving single ended or differentially doubly terminated transmission lines. The efficiency is in the reduced amount of current drawn from the supply for a given output swing across a doubly terminated transmission line. The driver is capable of pre-emphasis and dynamically controllable output swings.
In a first aspect the present invention provides a driver circuit including:
an input,
a voltage mode driver circuit connected in parallel with a current mode driver circuit, between a voltage source and ground,
the outputs of said voltage and current mode drivers being connected in parallel and to a transmission line.
In a second aspect the present invention provides a driver circuit comprising:
a pair of inputs comprising a first input and a second input;
a series terminated voltage mode driver sub-circuit;
at least one current mode driver sub-circuit;
a pair of outputs comprising a first output and a second output, wherein
each of the sub-circuits is coupled in parallel to each one of the pair of outputs;
at least two of the sub-circuits are coupled in parallel to each one of the pair of inputs.
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patent: 6005414 (1999-12-01), Reay
patent: 6025742 (2000-02-01), Chan
patent: 6111431 (2000-08-01), Estrada
patent: 6531896 (2003-03-01), Song
Hissen Jurgen
Lee Victor
Plasterer John Philip
Behmann Curtis B.
Borden Ladner Gervais LLP
PMC-Sierra Inc.
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