High efficiency memory device

Details High efficiency memory device High efficiency memory device

2000-03-03

2002-07-02

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S316000, C257S317000, C257S321000

Reexamination Certificate

active

06414349

ABSTRACT:

TECHNICAL FIELD
The invention relates to a high efficiency memory device, particularly of EEPROM type.
BACKGROUND OF THE INVENTION
As known, in electronics there is currently a demand for memory devices having ever-larger storage capacities without being of larger dimensions; this creates a demand for progressive miniaturization of the devices.
Consequently, manufacturing processes are being designed that enable the dimensions of the memory cells, particularly of EEPROM type, to be reduced; the lithographic processes for defining the various regions forming the cells do not, however, enable the dimensions of the cells to be reduced beyond a certain limit. Furthermore, the reduction of the area of each cell involves a similar reduction of the facing areas between the floating gate and control gate regions; consequently the coupling coefficient between these two gate regions is reduced, causing lower programming efficiency. This lower efficiency thus requires that the programming voltage be increased; this cannot, however, be increased beyond a certain limit, to prevent the risk of breakage of the cells.
SUMMARY OF THE INVENTION
The disclosed embodiments of the invention provide a memory device that overcomes the above drawbacks and, in particular, enables the facing area between the floating gate and control gate regions, and therefore the programming efficiency, to be increased.
The memory device includes at least one first memory cell having a memory transistor; the memory transistor having a first and a second gate region overlaid to each other and mutually insulated. The first and second gate region are arranged over and insulated from a substrate of semiconductor material of a first conductivity type. The memory transistor further includes a first and a second conductive region of a second conductivity type, both formed in the substrate respectively on a first and a second side of the first and second gate regions. The first and second gate regions and first and second conductive regions are mutually aligned along a longitudinal section plane. The second gate region has a non-constant width in different section planes parallel to the longitudinal section plane.


REFERENCES:
patent: 4868619 (1989-09-01), Mukherjee et al.
patent: 678921 (1995-10-01), None
patent: 04179167 (1992-06-01), None
patent: 07086438 (1995-03-01), None
patent: 07297303 (1995-11-01), None

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