High-efficiency error detection and/or correction code

Details High-efficiency error detection and/or correction code High-efficiency error detection and/or correction code

2007-04-10

2007-04-10

Torres, Joseph D. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

10115577

ABSTRACT:
A method for determining r error detection bits that can be associated with a word of m bits to be coded, including the step of calculating the product of a vector with m components representative of the word of m bits to be coded and of a parity control matrix of dimension r×m. The parity control matrix is such that each column of matrix includes an odd number of “1s” greater than or equal to three. The present invention also relates to a method for determining a syndrome.

REFERENCES:
patent: 3623155 (1971-11-01), Hsiao et al.
patent: 4862463 (1989-08-01), Chen
patent: 4888774 (1989-12-01), Kosuge et al.
patent: 5774481 (1998-06-01), Meaney et al.
patent: 0 310 220 (1995-05-01), None
Stephen B. Wicker, Error Control Systems for Digital Communication and Storage, Prentice-Hall, 1995.
Glick, E.W. et al., “Single-Error Correction, Double-Error Detection Code Utilizing Minimum Circuitry,”IBM Technical Disclosure Bulletin, 15(1):130-134, Jun. 1972.

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