Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Patent
1996-07-23
1998-02-10
Santamauro, John
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Output switching noise reduction
326 83, 326121, H03K 190948, H03K 1716
Patent
active
057173435
ABSTRACT:
A CMOS output buffer has a first stage with smaller driver transistors and a second stage having larger driver transistors. Both stages drive the output in parallel during the first half of a voltage transition, but the larger, second stage is disabled during the second half of the output voltage swing. The output voltage is fed back to an isolation circuit by a pulse generator which is triggered by the output reaching the switching threshold. The pulse generated disables the larger driver for a short period of time but later re-enables the driver. Thus the large driver remains on after the switching is complete, providing large IOH and IOL static currents. The pulse is long enough to keep the large driver disabled while reflections are received and ringing occurs after the voltage transition. Resistors in the smaller first stage absorb these reflections. The output impedance is pulsed to the higher impedance of the first stage when ringing occurs at the end of the voltage transition, but after the pulse ends the lower impedance of the large driver is seen. Pulses are sent to neighboring output buffers and are OR'ed together to disable adjacent output buffer's large drivers when noise in injected into the power or ground supplies.
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Auvinen Stuart T.
Pericom Semiconductor Corp.
Santamauro John
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