Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-10-23
2001-02-27
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S327000, C257S344000
Reexamination Certificate
active
06194768
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming a transistor upon a semiconductor substrate in which the gate length of a metal-based gate conductor which forms the transistor is dependent upon deposition rather than photolithography, and wherein the and the gate dielectric comprises a metal oxide having a relatively high dielectric constant.
2. Description of the Related Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline (“polysilicon”) material over a relatively thin gate oxide. The polysilicon material and the gate oxide are then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant species. If the impurity dopant species used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (“n-channel”) transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET (“p-channel”) transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used.
Patterning the polysilicon material to form the gate conductor occurs by a process called photolythography. Typically, a photolythography mask is used to allow select removal of a light-sensitive material deposited entirely across a layer of polysilicon. The material which is exposed can, according to one embodiment, be polymerized and that which is not exposed removed. Selective polymerization is often referred to as the “develop” step of lithography. The regions which are non-polymerized are removed using the etch stage of lithography.
Conventional lithography used to pattern a gate conductor suffers many drawbacks. For example, selective exposure is highly dependent upon accurately placing light on the light-sensitive material. Furthermore, the light-sensitive material must consistently respond to the light with fine-line resolution. Any elevational disparity on which the polysilicon resides will result in slight changes in the point at which light impinges on the light-sensitive material. This results in a variation of the polymerized
on-polymerized boundary.
It would be advantageous to form a gate conductor without having to rely upon conventional lithographic patterning techniques. The impetus behind wanting to change gate formation methodology is principally driven from the smaller gate sizes of modern day integrated circuits. As gate lengths and widths become smaller to accommodate higher density circuits, it is necessary that the relatively small gate conductors be accurately produced with minimal misalignment or size variation. Any changes in the placement and geometry of a gate conductor can have negative performance effects on the ensuring MOS transistor.
Along with the benefits of increased density, reduction in the gate lengths and widths may further benefit the speed of the ensuing integrated circuit. Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to reduce the turn on transistor threshold voltage, V
T
. Several factors contribute to V
T
, one of which is the gate-to-substrate capacitance. The higher the gate-to-substrate capacitance, the lower the V
T
of a transistor. The value of this capacitance is dependent upon the thickness of the gate oxide, and the relative permittivity of the gate oxide. Unfortunately, the relative permittivity, or dielectric constant, K, of the gate oxide limits the amount of gate-to-substrate capacitance that can be achieved when a transistor is in operation. Permittivity, &egr;, of a material reflects the ability of the material to be polarized by an electric field. The capacitance between two layers of conductive material separated by a dielectric is directly proportional to the permittivity of the dielectric. The permittivity of a material is typically described as its permittivity normalized to the permittivity of a vacuum, &egr;
o
. Hence, the relative permittivity or dielectric constant of a material is defined as:
K=&egr;/&egr;
o
Since oxide (i.e., silicon dioxide) has a relatively low K of approximately 3.7 to 3.8, the minimum value of V
T
, and thus the transistor switching speed must be somewhat sacrificed in order to promote capacitive coupling between the gate conductor and the substrate.
As mentioned above, the gate-to-substrate capacitance is also affected by the thickness of the gate oxide. Conventional transistors typically include an ultra thin gate oxide to reduce the gate-to-substrate capacitance, and thereby lower V
T
. The value of the gate-to-source voltage, V
GS
, required to invert the channel underneath the gate conductor such that a drive current, I
D
, flows between the source and drain regions of the transistor is decreased. Consequently, the switching speed (from off to on and vice versa) of the logic gates of an integrated circuit employing such transistors is faster, allowing the integrated circuit to quickly transition between logic states (i.e., operate at high frequencies).
Unfortunately, thin oxide films may break down when subjected to an electric field. Particularly, for a gate oxide which is less than 50 Å thick, it is probable that when V
GS
is equivalent to only 3V, electrons can pass through the gate oxide by what is known as the quantum mechanical tunneling effect. In this manner, a tunneling current may undesirably form between the semiconductor substrate and the gate conductor, adversely affecting the operability of the device. It is postulated that these electrons may become entrapped within the gate oxide by e.g., dangling bonds. As a result, a net negative charge density may form in the gate oxide. As the trapped charge accumulates with time, V
T
may shift from its design specification. Breakdown of the gate oxide may also occur at even lower values of V
GS
, as a result of defects in the gate oxide. Such defects are unfortunately prevalent in relatively thin gate oxides. For example, a thin gate oxide often contains pinholes and/or localized voids due to unevenness at which the oxide grows on a less than perfect silicon lattice. Low breakdown voltages also correlate with high defect density near the surface of the substrate.
In addition to advantages which might be gained in forming a gate conductor without relying on lithography limitations, it would be desirable to introduce a technique which can reduce gate-to-substrate capacitance so that the ensuing transistor is substantially resistant to gate dielectric breakdown. The improved technique would be one which avoids relatively thin gate oxide problems yet enjoys the advantage of a high speed operation necessary for modern integrated circuits. Tunneling currents formed between the gate dielectric and the gate conductor would be minimized along with a possibility of electrons becoming trapped within the gate dielectric. This affords an advantage in that the improved technique would produce a transistor that can operate at high speeds, is resistant to the limitations of photolithography as well as threshold skews from the desired V
T
value.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an improved transistor configuration hereof. The transistor can be either a p-channel or an n-channel transistor. The transistor is classified as one having a gate conductor formed outside the conventional lithography process. Instead of depositing a gate conductor material across an entire planar surface, the present process employs a gate conductor bounded in a localized region which extends from a lateral surface of a sacrificial structure. The bounded gate conductor can be formed by depositi
Gardner Mark I.
Hause Frederick N.
May Charles E.
Advanced Micro Devices , Inc.
Conley Rose & Tayon
Crane Sara
Daffer Kevin L.
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