High density vertical SRAM cell using bipolar latchup...

Details High density vertical SRAM cell using bipolar latchup... High density vertical SRAM cell using bipolar latchup...

1998-05-13

2003-04-08

Eckert, George (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Bidirectional rectifier with control electrode

C257S119000, C257S135000, C257S139000, C365S154000, C365S180000, C365S182000

Reexamination Certificate

active

06545297

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to non-volatile static memory devices. Particularly, this invention relates to a high density Static Random-Access Memory (SRAM) cell taking advantage of the latch-up phenomenon in a Complementary Metal Oxide Semiconductor (CMOS).
BACKGROUND OF THE INVENTION
One known type of static read/write memory cell is a high-density static random access memory (SRAM). A static memory cell is characterized by operation in one of two mutually-exclusive and self-maintaining operating states. Each operating state defines one of the two possible binary bit values, zero or one. A static memory cell typically has an output which reflects the operating state of the memory cell. Such an output produces a “high” voltage to indicate a “set” operating state. The memory cell output produces a “low” voltage to indicate a “reset” operating state. A low or reset output voltage usually represents a binary value of zero, while a high or set output voltage represents a binary value of one.
A static memory cell is said to be bistable because it has two stable or self-maintaining operating states, corresponding to two different output voltages. Without external stimuli, a static memory cell will operate continuously in a single one of its two operating states. It has internal feedback to maintain a stable output voltage, corresponding to the operating state of the memory cell, as long as the memory cell receives power.
The operation of a static memory cell is in contrast to other types of memory cells such as dynamic cells which do not have stable operating states. A dynamic memory cell can be programmed to store a voltage which represents one of two binary values, but requires periodic reprogramming or “refreshing” to maintain this voltage for more than very short time periods.
A dynamic memory cell has no internal feedback to maintain a stable output voltage. Without refreshing, the output of a dynamic memory cell will drift toward intermediate or indeterminate voltages, resulting in loss of data. Dynamic memory cells are used in spite of this limitation because of the significantly greater packaging densities which can be attained. For instance, a dynamic memory cell can be fabricated with a single MOSFET transistor, rather than the six transistors typically required in a static memory cell.
One of the limitations of static memory cells utilizing both n-channel and p-channel devices (CMOS SPAMS) is their exceptionally large cell areas, typically over 100 F
2
, where F is the minimum feature size. Even using only n-channel devices, cell size in a compact SRAM design is over 5F
2
. See U.S. Pat. No. 5,486,717. The result is much lower densities than for DRAMs, where the cell size is only 6 or 8 F
2
.
Conventional CMOS SRAM cells essentially consist of a pair of cross-coupled inverters as the storage flip-flop or latch, and a pair of pass transistors as the access devices for data transfer into and out of the cell. Thus, a total of six Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), or four MOSFETs plus two very high resistance load devices, are required for implementing a conventional CMOS SRAM cell.
To achieve higher packing densities, several methods are known for reducing the number of devices needed for CMOS SRAM cell implementation, or the number of the devices needed for performing the Read and Write operations. However, increased process complexity, extra masks, and high fabrication cost are required and the corresponding product yield is not high.
For example, K. Sakui, et al., “A new static memory cell based on reverse base current (RBC) effect of bipolar transistor,” IEEE IEDM Tech. Dig., pp. 44-47, December 1988), refers to a Bipolar-CMOS (BICMOS) process in which only two devices are needed for a SRAM cell: one vertical bipolar transistor, and one MOSFET as a pass device. Extra processing steps and increased masks are required, along with special deep isolation techniques, resulting in high fabrication cost and process complexity. Yield of SRAM products utilizing such complex processes is usually low compared with the existing CMOS processes.
A problem with CMOS circuits in general is their propensity to “latchup.” Latchup is a phenomenon that establishes a very low-resistance path between the V
DD
and V
SS
power lines, allowing large currents to flow through the circuit. This can cause the circuit to cease functioning, or even to destroy itself due to heat damage caused by high power dissipation.
The susceptibility to latchup arises from the presence of complementary parasitic bipolar transistor structures, which result from the fabrication of the complementary MOS devices in CMOS structures. Since they are in close proximity to one another, the complementary bipolar structures can interact electrically to form device structures which behave like p-n-p-n diodes. In the absence of triggering currents, such diodes act as reverse-biased junctions and do not conduct. Such triggering currents, however, may be and in practice are established in any one or more of a variety of ways, e.g., terminal overvoltage stress, transient displacement currents, ionizing radiation, or impact ionization by hot electrons.
Gregory, B. L., et al., “Latchup in CMOS integrated circuits,”
IEEE Trans. Nuci. Sci.
(USA), Vol. 20, no. 6, p. 293-9, proposes several techniques designed to eliminate latchup in future CMOS applications. Other authors, such as Fang, R. C., et al., “Latchup model for the parasitic p-n-p-n path in bulk CMOS,”
IEEE Transactions on Electron Devices
, Vol. ED-31, no. 1, pp. 113-20, provide models of the latchup phenomenon in CMOS circuits in an effort to facilitate design optimizations avoiding latchup.
The present invention takes advantage of the normally undesirable latchup phenomenon in CMOS circuits to construct a compact static memory cell.
SUMMARY OF THE INVENTION
The present invention provides area efficient static memory cells and memory arrays by the use of parasitic bipolar transistors which can be latched in a bistable on state with small area transistors. Each bipolar transistor memory cell includes a gate which is pulse biased during the write operation to latch the cell. These cells can be realized utilizing CMOS technology to create vertical structures in trenches with a minimum of masking steps and minimal process complexity.


REFERENCES:
patent: 3623029 (1971-11-01), Davidson et al.
patent: 4636830 (1987-01-01), Bhagat
patent: 4882706 (1989-11-01), Sinclair
patent: 5173754 (1992-12-01), Manning
patent: 5214295 (1993-05-01), Manning
patent: 5286663 (1994-02-01), Manning
patent: 5412598 (1995-05-01), Shulman
patent: 5471419 (1995-11-01), Sankaranarayanan et al.
patent: 5486717 (1996-01-01), Kokubo et al.
patent: 5497011 (1996-03-01), Terashima
patent: 5535156 (1996-07-01), Levy et al.
patent: 5581104 (1996-12-01), Lowrey et al.
patent: 5594683 (1997-01-01), Chen et al.
patent: 5615143 (1997-03-01), MacDonald et al.
patent: 5624863 (1997-04-01), Helm et al.
patent: 5650350 (1997-07-01), Dennison et al.
patent: 5684737 (1997-11-01), Wang et al.
patent: 5705843 (1998-01-01), Roberts
patent: 5710741 (1998-01-01), McLaury
patent: 5981984 (1999-11-01), Iwaana et al.
Ng, K. K., Complete Guide to Semiconductor Devices, pp. 337-344, 1995.*
Wolf, S., Silcon Processing for the VLSI Era, vol. 2, pp. 400-408, 1990.*
R. C. Fang, Latchup Model for the Parasitic P-N-P-N Path in Bulk CMOS, IEEE Transactions on Electron Devices, vol. Ed. 31, No. 1, Jan. 1984.
R. R. Troutman et al, Transient Analysis of Latchup in Bulk CMOS, IEEE Transactions on Electron Devices, vol. Ed. 30, No. 2, Feb. 1993.
D. L. Hetherington et al, An Integrated GaAs N-P-N-P Thyristor/JFET Memory Cell Exhibiting Nondestructive Read, IEEE Electron Device Letters, vol. 13, No. 9, Sep. 1992.
S. V. Vandebroek et al, High-Gain Lateral Bipolar Action in a MOSFET Structure, IEEE Transactions on Electron Devices, vol. 38, No. 11, Nov. 1991.
Dermot MacSweeney et al., Modeling of Lateral Bipolar Devices in a CMOS, IEEE BCTM 1.4, 4 pages.
J.J. Ebers, Four-Terminal P-N-

Affiliated with

Also associated with

Rating

High density vertical SRAM cell using bipolar latchup... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High density vertical SRAM cell using bipolar latchup..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High density vertical SRAM cell using bipolar latchup... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3003535