High density three dimensional semiconductor die package

Details High density three dimensional semiconductor die package High density three dimensional semiconductor die package

2005-11-02

2010-02-16

Andújar, Leonardo (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S684000, C257S735000

Reexamination Certificate

active

07663216

ABSTRACT:
A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates. By providing each flash memory semiconductor die on a substrate with a unique layout of address traces, each memory die may be selectively addressed by the controller die.

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patent: 2001/0009505 (2001-07-01), Nishizawa et al.
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International Search Report dated May 31, 2007 in PCT Application No. PCT/US2006/042664.
Chinese Office Action dated Aug. 27, 2009 in Chinese Patent Application No. 200680045630.4.

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