High density SRAM cell with latched vertical transistors

Details High density SRAM cell with latched vertical transistors High density SRAM cell with latched vertical transistors

2006-09-12

2006-09-12

Graybill, David E. (Department: 2822)

Semiconductor device manufacturing: process

Making regenerative-type switching device

Having field effect structure

C438S212000, C438S237000, C438S238000

Reexamination Certificate

active

07105386

ABSTRACT:
High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.

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