Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1996-02-09
1999-07-20
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711104, 711106, 711 5, 365193, 36523002, 36523003, 36523006, 365222, G06F 1200
Patent
active
059268271
ABSTRACT:
The signal configuration for addressable DRAMs from a system is changed from a signal that actuates a single bank of DRAMs having Y/X row/column addresses actuated by a single RAS, to a signal configuration that provides two RAS signals for two banks of DRAMs having Y-1/X row/column addresses actuated by two RAS signals. This is done by converting the high order address bit from the system to a RAS signal actuated by a system RAS when, and only when, the high order bit is of a given value.
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patent: 5596741 (1997-01-01), Thome
patent: 5600604 (1997-02-01), Chen
patent: 5613094 (1997-03-01), Khan
Dell Timothy Jay
Hazelzet Bruce Gerard
Kellogg Mark William
Cabeca John W.
Hogg William N.
International Business Machines Corp.
Tran Denise
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