High density semiconductor memory cell and memory array...

Details High density semiconductor memory cell and memory array... High density semiconductor memory cell and memory array...

2002-04-26

2004-08-17

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S390000, C257SE27080, C257S005000, C365S177000, C365S178000

Reexamination Certificate

active

06777757

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile programmable semiconductor memory, and more particularly to a single transistor memory cell programmed by break down of the transistor gate oxide, and a memory array incorporating such cells.
BACKGROUND OF THE INVENTION
Nonvolatile memory retains stored data when power is removed, which is desirable in many different types of electronic devices. One commonly available type of nonvolatile memory is the programmable read-only memory (“PROM”), which uses word line—bit line crosspoint elements such as fuses, anti-fuses, and trapped charge devices such as the floating gate avalanche injection metal oxide semiconductor (“FAMOS”) transistor to store logical information.
An example of one type of PROM cell that uses the breakdown of a silicon dioxide layer in a capacitor to store digital data is disclosed in U.S. Pat. No. 6,215,140 to Reisinger et al. The basic PROM disclosed by Reisinger et al. uses a series combination of an oxide capacitor and a junction diode as the crosspoint element (the term “crosspoint” refers to the intersection of a bitline and a wordline). An intact capacitor represents the logic value 0, and an electrically broken-down capacitor represents the logic value 1. The thickness of the silicon dioxide layer is adjusted to obtain the desired operation specifications. Silicon dioxide has a breakdown charge of about 10 C/cm
2
(Coulomb/cm
2
). If a voltage of 10 volts is applied to a capacitor dielectric with a thickness of 10 nm (resultant field strength 10 mV/cm), a current of about 1 mA/cm
2
flows. With 10 volts, this thus results in a substantial amount of time for programming a memory cell. However, it is more advantageous to design the capacitor dielectric to be thinner, in order to reduce the high power loss which occurs during electrical breakdown. For example, a memory cell configuration having a capacitor dielectric with a thickness of 3 to 4 nm can be operated at about 1.5 V. The capacitor dielectric does not yet break down at this voltage, so that 1.5 V is sufficient to read data from the memory cell. Data are stored, for example, at 5 V, in which case one cell strand in a memory cell configuration can be programmed within about 1 millisecond. The energy loss which occurs in this case per cm
2
of capacitor dielectric is then about 50 Watts (10 Coulomb*5 V). If the desired power loss is about 0.5 W, about 100 seconds are required to program a 1 Gigabit memory. If the permissible power losses are higher, the programming can be carried out correspondingly more quickly.
Some types of nonvolatile memory are capable of being repeatedly programmed and erased, including erasable programmable read only semiconductor memory generally known as EPROM, and electrically erasable programmable read only semiconductor memory generally known as EEPROM. EPROM memory is erased by application of ultraviolet light and programmed by application of various voltages, while EEPROM memory is both erased and programmed by application of various voltages. EPROMs and EEPROMs have suitable structures, generally known as floating gates, that are charged or discharged in accordance with data to be stored thereon. The charge on the floating gate establishes the threshold voltage, or V
T
, of the device, which is sensed when the memory is read to determine the data stored therein. Typically, efforts are made to minimize gate oxide stress in these types of memory cells.
A device known as a metal nitride oxide silicon (“MNOS”) device has a channel located in silicon between a source and drain and overlain by a gate structure that includes a silicon dioxide layer, a silicon nitride layer, and an aluminum layer. The MNOS device is switchable between two threshold voltage states V
TH(high)
and V
TH(low)
by applying suitable voltage pulses to the gate, which causes electrons to be trapped in the oxide-nitride gate (V
TH(high)
) or driven out of the oxide-nitride gate (V
TH(low)
). Again, efforts are made to minimize gate oxide stress in these types of memory cells.
A junction breakdown memory cell that uses a stored charge on the gate of a gate controlled diode to store logic 0 and 1 values is disclosed in U.S. Pat. No. 4,037,243 to Hoffman et al. Charge is stored on the gate by using a capacitance formed between the p-type electrode of the gate controlled diode and the gate electrode. Charge storage is enhanced by using a composite dielectric in the capacitor formed from silicon dioxide and silicon nitride layers in place of silicon dioxide. The application of an erase voltage to the electrode of the gate controlled diode causes the oxide-nitride interface surface to fill with negative charge, which is retained after the erase operation is completed. This negative interface charge causes the gate controlled diode to operate in an induced junction mode even after the erase voltage is removed. When the gate controlled diode is thereafter read, it exhibits field-induced junction breakdown of its channel and a saturation current flows. The field induced junction breakdown voltage is less than the metallurgical junction breakdown voltage. However, the application of a write voltage to the electrode of the gate controlled diode causes the silicon dioxide/silicon nitride interface to fill with positive charge, which is retained after the write operation is completed. When the gate controlled diode is thereafter read, it will not break down because no channel exists. Only a slight current flows. The different current flows are sensed and indicate different logic states.
Improvements in the various processes used for fabricating the various types of nonvolatile memory tend to lag improvements in widely used processes such as the advanced CMOS logic process. For example, processes for devices such as flash EEPROM devices tend to use 30% more mask steps than the standard advanced CMOS logic process to produce the various special regions and structures required for the high voltage generation circuits, the triple well, the floating gate, the ONO layers, and the special source and drain junctions typically found in such devices. Accordingly, processes for flash devices tend to be one or two generations behind the standard advanced CMOS logic process and about 30% more expensive on a cost-per-wafer basis. As another example, processes for antifuses must be suitable for fabricating various antifuse structures and high voltage circuits, and so also tend to be about one generation behind the standard advanced CMOS process.
Generally, great care is taken in the fabrication of the silicon dioxide layer used in metal-oxide-silicon (MOS) devices such as capacitors and transistors. The high degree of care is necessary to ensure that the silicon dioxide layer is not stressed during manufacture or subsequent normal operation of the integrated circuit, so that the desired device characteristics are attained and are stable over time. One example of how much care is taken during fabrication is disclosed in U.S. Pat. No. 5,241,200 to Kuroda, which discloses the use of a diffused layer and a shunt to discharge charges accumulated in the word line during a wafer fabrication process. Avoiding this charge accumulation ensures that a large electric field is not applied to the gate insulating film, so that variations in the characteristics of transistors using the word line as their gate wiring line and degradation and breakdown of the gate insulating film are prevented.
An example of how much care is taken in circuit design to avoid stressing the silicon dioxide layer of a transistor during normal circuit operation is disclosed in U.S. Pat. No. 6,249,472 to Tamura et al. Tamura et al. disclose an antifuse circuit having an antifuse in series with a p-channel MOS transistor in one embodiment and in series with an n-channel MOS transistor in another embodiment. While the antifuse is fabricated without the additional film manufacturing processes typically required for fabricating antifuse circuits, Tamura et al. poses another problem. When the a

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