High density self-aligned stack in trench DRAM technology

Details High density self-aligned stack in trench DRAM technology High density self-aligned stack in trench DRAM technology

1995-04-24

1997-01-14

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Capacitors

257301, 257296, G11C 1124

Patent

active

055946828

ABSTRACT:
A method, and resultant structure, is described for fabricating a high density DRAM cell in which a stacked capacitor using a pillar structure is formed in a trench. The DRAM cell includes a field effect transistor having a gate electrode and source/drain elements. A first insulating layer is patterned to create an exposed region wherein a first trench is formed in the silicon substrate, between the gate electrode and the field oxide. A second insulating layer is formed, and then removed from a portion of the bottom of the first trench to expose the silicon substrate. The silicon substrate is thermally oxidized at the bottom of the first trench to form an insulating layer mask. The remainder of the second insulating layer is removed. The portion of the silicon substrate in the first trench that is not masked by the insulating layer mask is vertically etched, whereby a pillar is formed under the insulating layer mask in the center of the final trench. The insulating layer mask is removed. A conductive layer is formed along the surfaces of the final trench and the pillar, adjacent to the source region of the field effect transistor, whereby the conductive layer is a capacitor signal node. A capacitor dielectric is formed over the conductive layer. A capacitor ground plate is formed over the capacitor dielectric.

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"A 0.6 .mu.m.sup.2 256Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST)" by L. Nesbit et al. pp. 627-630, Tech. Dig of IEDM, 1993.

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