High density read only memory

Details High density read only memory High density read only memory

2001-06-29

2002-10-08

Tsai, Jey (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S330000, C257S320000

Reexamination Certificate

active

06462387

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor manufacturing process and more particularly to a high density read only memory (HDROM) and fabrication method thereof.
BACKGROUND OF THE INVENTION
Semiconductor fabrication technology have known a rapid and a spectacular development leading from sub micron fabrication to deep-sub micron fabrication. The size of thus produced semiconductor device is even smaller. As a result, the size of chip is decreased and the number of chips formed on each wafer is increased. And in turn the fabrication cost of each chip is reduced as the number and operating speed of transistors on a chip are increased. The number of transistors is double every one and half year based on Morgan's theory. As such, memory size of an integrated circuit (IC) has increased from past several thousand bits per chip to current several ten million bits per chip. In the case of read only memory (ROM), there are ICs having 1 Giga-bit capacity available now. Currently, ROMs having 64 million-bit are the most popular one.
In view of this trend, ROM capacity and operating speed will be higher as time goes as required by electronic product manufacturers. Hence, it is obvious that high density high capacity ROMs are the main stream of development. It is also anticipated that high density ROMs will replace current semiconductor products as the dominant product in the near future. As such, most semiconductor manufacturers endeavor to develop such products.
Currently, a NAND gate based architecture is incorporated in each cell of existing HDROMs for decreasing the number of contacts. It is advantageous for decreasing the area of chip. It is disadvantageous, however that resistance of serially connected cells becomes large by incorporating such NAND gate architecture. As such, a RC delay is occurred due to increase of resistance value (R) of the serially connected cell. And in turn the speed of reading, writing, or erasing is slowed. Further, ROMs having such NAND gates are fabricated by utilizing Fowler-Nordheim tunneling or hot carrier writing principle. Hence, cells tend to over program, thus causing the number of electrons in floating gate to increase excessively. As a result, critical threshold voltage of the conventional ROM cell is increased beyond control which in turn causes the channel of cell to be cut off permanently. Hence, such conventional HDROMs are limited in electronic applications. Thus improvement exists.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a high density read only memory and fabrication method thereof. The method comprises the step of fabricating a plurality of spaced post transistors on a wafer by implanting and trench etching wherein each post transistor has four vertical surfaces with one of vertical surfaces as a short circuit junction between substrate and source and a read only memory (ROM) cell formed on each of the three remaining vertical surfaces. This can maintain a critical threshold voltage on transistors of ROM cells at the same level while there is a voltage drop between substrate and source thereof. Further, in the layout of ROM cells drains of ROM cells are alternately coupled together because a word line is shared by adjacent ROM cells. Therefore, the invention can fabricate three ROM cells in a single post transistor for storing three-bit data, thereby fabricating high density ROM cells.
The above and other objects, features and advantages of the present invention will become apparent from the following detailed description taken with the accompanying drawings.


REFERENCES:
patent: 5747856 (1998-05-01), Chen et al.

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