Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1998-06-08
2001-07-03
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S266000
Reexamination Certificate
active
06255205
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority, pursuant to Title 35, United States Code §119, from Taiwanese Pat. No. 111452, issued Apr. 10, 1998, and filed on Aug. 6, 1997 as Application No. 86111278 and assigned to Mosel Vitelic, Inc. Taiwanese Pat. No. 111452 is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to the field of semiconductor electronic devices and the method for manufacturing the same. More particularly, the present invention relates to a process suited for manufacturing flash erasable programmable read-only memory cells.
Erasable programmable read-only memory (EPROM) technology is well known for use in both memory and programmable logic applications. In particular, EPROMs are implemented using floating gate field effect transistors in which the binary states of the EPROM cell are represented by the presence or absence, on the floating gate, of sufficient charge to prevent conduction even when a normal high signal is applied to the gate of the EPROM transistor.
In the traditional and most basic form, EPROMs are programmed electrically and erased by exposure to ultraviolet light. These EPROMs are typically referred to as ultraviolet erasable programmable read-only memories (UVPROMs). UVPROMs are programmed by running a high current between the drain and the source of the UVEPROM transistor while applying a positive potential to the gate. The positive potential on the gate attracts energetic (“hot”) electrons from the drain-to-source current, which jump onto the floating gate in an attempt to reach the gate and become trapped on the floating gate.
Another form of EPROM is the electrically erasable programmable read-only memory (EEPROM or E
2
PROM). EEPROMs generally include two serially connected N-channel metal oxide semiconductor transistors, in which one of the transistors has an additional control gate that is floating and is sandwiched between the gate and the channel. This gate is used to store positive or negative charges which determine the state of the EEPROM. The other transistor is used for selection purposes. The charging of the floating gate is done by Fowler-Nordheim tunneling of electrons out of or into the floating gate. The oxide layer between the channel and the floating gate is around 100 Å as reported in some converted devices. These conventional EEPROM occupy large spaces due to the large capacitive coupling that is required between the floating gate and the control gate. Efforts have been made, however, to increase the density of EEPROMs to enhance performance as well as decrease the per unit cost of the device.
For example, an improved EPROM is charged in a manner similar to the UVEPROM and erased in a manner similar to the EEPROM discussed above, typically referred to as a flash EEPROM. This improved type of EPROM is typically of smaller size than the traditional EPROM due to, inter alia, the arrangement of metal bit line contacts. As seen in
FIGS. 1 and 2
, a conventional improved EPROM array includes a series of metal bit lines which are formed so that each contacts the drain regions in one column of drain regions. The metal bit line-to-drain contacts, however, poses a significant challenge to further increasing the density of the array.
Typically, excess area between metal contacts and poly regions is generally required when forming the metal contacts to compensate for masking alignment error which may occur during the fabrication. This results in increased cell size. The metal bit line-to-drain contacts are formed by forming a contact mask over a layer of insulation material ILD to define a series of metal contact openings. The unmasked portions of the layer of insulation material ILD is etched to expose a portion of each of the drain regions. A layer of aluminum or tungsten (W) is deposited into the exposed drain region to form the metal bit line-to-drain contacts. Then, masking and etching of the layer of aluminum is performed to form each of the individual metal bit lines. Were the contact mask misaligned, the subsequent etching of the layer of insulation material ILD would expose a portion of the word line which could result in the floating gate and the word line shorting together, destroying the cell. To avoid this problem, the drain regions of the array are formed larger than otherwise would be necessary to avoid etching of the floating gate should mask misalignment occur.
U.S. Pat. Nos. 5,589,412 and 5,484,741 to Iranmanesh et al. and Bergemont, respectively, each discloses a method of increasing the density of a flash EPROM that utilizes a series of self-aligned intermediate strips of conductive material to form contacts to drain regions of field effect transistors (FETs). The aforementioned references disclose, in pertinent part, forming a plurality of stacked gate structures on a layer of gate dielectric material disposed over a substrate having the requisite doped regions to function as the source and drain of a field effect transistor (FET). A plurality of word lines are formed on field oxide regions, located within the substrate, as well as the stacked gate structures so that each word line is formed over and interconnects all of the stacked gate structures in one row of stacked gate structured. A layer of first insulation material is formed over each word line. A plurality of strips of second insulation materia are formed so that each strip of the second insulation material is formed over one common source bit line. A plurality of strips of spacer material are formed so that each strip of spacer material covers a portion of each drain region. A plurality of intermediate interconnect strips are formed over the strips of second insulation material, the strips of spacer material, the layers of first insulation material, and the drain regions to that each intermediate interconnect strip interconnects each drain region in one column of drain regions. A third layer in insulation material is formed over the strips of second insulation material, the strips of spacer material, the word lines, the substrate and the intermediate interconnect strips. The third layer of insulation material has a plurality of spaced-apart openings formed therein to expose portions of one intermediate interconnect strip. A drawback with the prior art attempts to increase the density of an EPROM array is that each after requires additional process steps which increases the cost of the device.
What is needed, therefore, is an improved method and apparatus that allows reducing the area required for forming contacts in an EPROM device without increasing the cost of producing the same.
SUMMARY OF THE INVENTION
The present invention provides an EPROM, a flash EPROM, an E
2
PROM and a method for forming the same having increased density. The invention does so by reducing the area after required for formation of a contact. Specifically, a storage cell for electrically programmable read-only memory (EPROM) includes a pair of spaced-apart gate structures, with a double wall spacer structure disposed about each gate structure A dielectric region is disposed atop, and extends coextensive with, each of the pair of spaced apart gate structures. In this manner, a pair of spaced apart insulated gate structures may be formed with an intermetal dielectric layer positioned atop thereof. An aperture is formed in the intermetal dielectric layer so as to be in superimposition with a portion of each of the pair of insulated gate structures and a region of the substrate disposed therebetween. A metallic contact layer, including a plug portion, disposed within the aperture, is formed atop of the intermetal dielectric layer, forming a metallic contact.
The metallic contact is self-aligned with the exposed region of the substrate by the double wall spacer and the dielectric region. Preferably, the double wall spacer is produced by forming adjacent to each of the pair of spaced-apart gate structures and the dielectric region disposed thereon, a pair of silicon oxide sidewall spacers. F
Booth Richard
Mosel Vitelic Inc.
Townsend and Townsend / and Crew LLP
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