High density planar SRAM cell using bipolar latch-up and gated d

Details High density planar SRAM cell using bipolar latch-up and gated d High density planar SRAM cell using bipolar latch-up and gated d

1998-05-13

2000-08-15

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Combined with field effect transistor

257140, 257162, 257903, 257175, 257180, 365180, 365175, H01L 2974, H01L 2711

Patent

active

061040452

ABSTRACT:
Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.

REFERENCES:
patent: 4543595 (1985-09-01), Vora
patent: 4720845 (1988-01-01), Lechner
patent: 5173754 (1992-12-01), Manning
patent: 5214295 (1993-05-01), Manning
patent: 5286663 (1994-02-01), Manning
patent: 5486717 (1996-01-01), Kokubo et al.
patent: 5497011 (1996-03-01), Terashima
patent: 5535156 (1996-07-01), Levy et al.
patent: 5581104 (1996-12-01), Lowry et al.
patent: 5594683 (1997-01-01), Chen et al.
patent: 5624863 (1997-04-01), Helm et al.
patent: 5650350 (1997-07-01), Dennison et al.
patent: 5684737 (1997-11-01), Wang
patent: 5705843 (1998-01-01), Roberts
patent: 5710741 (1998-01-01), McLaury
D. L. Hetherington et al, An Integrated GaAs N-P-N-P Thyristor/JFET Memory Cell Exhibiting Nondestructive Read, IEEE Electron Device Letters, vol. 13, No. 9, Sep. 1992.
S. V. Vandebroek et al, High-Gain Lateral Bipolar Action in a MOSFET Structure, IEEE Transactions on Electron Devices, vol. 38, No. 11, Nov. 1991.
J.J. Ebers, Four-Terminal P-N-P-N Transistors, Proceedings of IRE, Nov. 1952, pp. 1361-1364.
I.T. Ho et al, Single Thyuristor Static Memory and its Fabrication, vol. 23, No.3, 1980.
S. M. Sze, Physics of Semiconductor Devices, Second Edition, A Wiley Interscience Pub. 1981.
S.D. Malaviya, Single-Device DC Stable Memory Cell, IBM Technical Disclosure Bulletin, vol. 20, No. 9, pp. 3492-3494, Nov. 1978.
R. C. Fang, Latchup Model for the Parasitic P-N-P-N Path in Bulk CMOS, IEEE Transactions on Electron Devices, vol. Ed. 31, No. Jan. 1984.
R. R. Troutman et al. Transient Analysis of Latchup in Bulk CMOS, IEEE Transactions on Electron Devices, vol. Ed. 30, No. 2, Feb. 1993.
Farid Nemati et al, "A Novel High Density, Low Voltage SRAM Cell With a Vertical NDR Device", Center for Integrated Systems, Stanford University, CA, (2 pages).
Hyun-Jin Cho et al, "A Novel Pillar DRAM Cell for 4GBIT and Beyond", Center for Integrated Systems, Stanford University, CA, (2 pages).
(For both A and B citations above--published in IEEE 1998, Symposium on VLSI Technology, Honolulu, Hawaii, Jun. 9th and 11th, 1998).

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