Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-07-20
2001-04-03
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185180, C365S185190, C365S185240
Reexamination Certificate
active
06212101
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to flash memory devices, and more particularly to a high-density NOR-type flash memory device which operates at very low power supply voltage, and to a method of programming the memory device.
BACKGROUND OF THE INVENTION
Flash memories are commonly employed in a wide variety of computer systems to provide nonvolatile information storage. Conventional flash memories typically include program circuitry for programming information into the flash memory cells as well as erase circuitry for erasing the memory cells. However, the voltage levels required by such program and erase circuitry differ from the power supply voltage levels that are typically available from a computer system power supply voltage.
Some flash memories require multiple voltage supplies to accommodate the program and erase circuitry. For example, any flash memory requires a power supply voltage and a separate high voltage for the program circuitry. Unfortunately, such a requirement of dual voltage supplies typically increases the complexity of power system design for computer systems that employ such dual supply flash memories and increases the overall cost of such systems.
On the other hand, single power supply flash memories commonly contain specialized circuitry that generates the appropriate voltage levels and electrical current levels required to program and erase the individual flash memory cells. For example, such flash memories typically include charge pump circuitry that converts a single electrical supply voltage into the appropriate voltage level required to drive the inputs to the flash memory cells during programming.
More recent computer systems, such as portable computers, employ integrated circuits and other devices that function with relatively low power supply voltage levels in comparison to earlier systems. For example, conventional notebook computer systems that employed 5V power supply voltage are now evolving toward 3V or lower power supply voltages (for example, 2V or 1.5V).
Unfortunately, such low levels of electrical power supply voltages impose a practical limit on the amount of electrical programming current that can be generated by charge pump circuitry on the flash memory. Such a limit on available programming current may reduce the overall speed of such flash memories by limiting the number of flash cells that can be programmed simultaneously.
Theoretically, a larger and more complex implementation of charge pump circuitry would provide the necessary electrical current required to program entire bytes or words of flash memory cells simultaneously. If the voltage level of the power supply voltage is further reduced, for example, if it is lowered below 2V, the charge pump circuitry becomes much more complicated and much larger. Such large and complex charge pump circuitry consumes large areas of an integrated circuit die. Such large amounts of integrated circuit die space dedicated to charge pump typically reduces the area available for flash memory cells and associated access circuitry, which thereby limits the overall storage capacity of such a flash memory. On the other hand, such large amounts of die space may require a significant increase in the overall size of the integrated circuit die which increases manufacturing costs.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a high-density NOR-type flash memory device capable of reducing the size of charge pump by minimizing maximum operating current consumed during programming, and to provide its programming method.
It is another object of the invention to provide a high-density NOR-type flash memory device which can shorten program time, and to provide its programming method.
In order to attain the above objects, according to an aspect of the present invention, there is provided a NOR-type flash memory device, which comprises an array of a plurality of memory cells arranged in rows and columns, a row-selecting circuit for selecting one of the rows, and a column-selecting circuit for selecting ones of a group among the columns. In the memory device, a pump circuit is provided which generates a drain voltage to be supplied to the selected columns during a program operation. Furthermore, the memory device provides a program period control circuit, a select circuit and a write driver circuit. The program period control circuit generates first and second program period signals indicating a program period of memory cells assigned by the selected row and columns. The select circuit generates select signals assigning the selected columns respectively in response to the first and second program period signals and data bits to be programmed to the assigned memory cells. And the write driver circuit drives the selected columns with the drain voltage from the pump circuit in response to the select signals.
In this embodiment, the program period control circuit generates the first program period signals each corresponding to the assigned memory cells so that the assigned memory cells are sequentially programmed up to a predetermined threshold voltage which is less than a target threshold voltage; and wherein the program period control circuit generates the second program period signal so that the assigned memory cells are simultaneously programmed up to the target threshold voltage from the predetermined threshold voltage.
In this embodiment, the first drain voltage has a different level from a second drain voltage, the first drain voltage being supplied to the selected columns during a first time when the assigned memory cells are programmed up to the predetermined threshold voltage, and the second drain voltage being supplied to the selected columns during a second time when the assigned memory cells are programmed up to the target threshold voltage from the predetermined threshold voltage.
In this embodiment, the second drain voltage is higher than the first drain voltage, and a unit program time of each of the selected memory cells is identical to a sum of the first time and the second time.
REFERENCES:
patent: 6101125 (2000-08-01), Gorman
Hoang Huan
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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