High density MOS technology power device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257139, 257342, 257401, H01L 2976, H01L 2974

Patent

active

060547375

ABSTRACT:
A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulating material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes a first elongated window in the conductive material layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a second insulating material layer disposed above the conductive material layer and disposed along elongated edges of the first elongated window. The second insulating material layer includes a second elongated window extending above each elongated body region. The second insulating material layer seals the edges of the conductive material layer from a source metal layer disposed over the second insulating material layer. The source metal layer contacts each body region and each source region through each second elongated window along the length of the elongated body region.

REFERENCES:
patent: 4015278 (1977-03-01), Fukuta
patent: 4055884 (1977-11-01), Jambotkar
patent: 4145700 (1979-03-01), Jambotkar
patent: 4344081 (1982-08-01), Pao et al.
patent: 4345265 (1982-08-01), Blanchard
patent: 4399449 (1983-08-01), Herman et al.
patent: 4412242 (1983-10-01), Herman et al.
patent: 4414560 (1983-11-01), Lidow
patent: 4642666 (1987-02-01), Lidow et al.
patent: 4705759 (1987-11-01), Lidow et al.
patent: 4716126 (1987-12-01), Cogan
patent: 4798810 (1989-01-01), Blanchard et al.
patent: 4816882 (1989-03-01), Blanchard et al.
patent: 4931408 (1990-06-01), Hshieh
patent: 4959699 (1993-10-01), Lidow et al.
patent: 4974059 (1990-11-01), Kinzer
patent: 5015593 (1991-05-01), Yawata et al.
patent: 5031009 (1991-07-01), Fujihira
patent: 5043781 (1991-08-01), Nishiura et al.
patent: 5119153 (1992-06-01), Korman et al.
patent: 5130767 (1992-07-01), Lidow et al.
patent: 5191396 (1993-03-01), Lidow et al.
patent: 5338961 (1994-08-01), Lidow et al.
patent: 5397728 (1995-03-01), Sasaki et al.
patent: 5418179 (1995-05-01), Hotta
patent: 5426320 (1995-06-01), Zambrano
patent: 5442216 (1995-08-01), Gough
patent: 5508217 (1996-04-01), Sawada
patent: 5563436 (1996-10-01), Barret et al.
patent: 5621234 (1997-04-01), Kato
patent: 5631483 (1997-05-01), Ferla et al.
patent: 5670392 (1997-09-01), Ferla et al.
patent: 5731604 (1998-03-01), Kinzer
European Search Report from European Patent Application No. 95830453.7, filed Oct. 30, 1995.
Stanford Electronics Laboratories, Integrated Circuits Laboratory, Stanford University, Stanford, Ca, Technical Report No. 4956-1, Mar. 1976, Michael Donald Pocha, "High Voltage Double Diffused MOS Transistors for Integrated Circuits" pp. 229-240.
IEEE Journal of Solid-State Circuits, vol. SC-11, No. 4, Aug. 1976, Isao Yoshida, et al., "A High Power MOSFET With a Vertical Drain Electrode And A Meshed Gate Structure", pp. 472-477.
Siliconix Technical Proposal in response to N.A.F.I., Solicitation #N00163-77-R-1197, Aug. 31, 1977, Labor And Materials to Design, Develop and Fabricate a 500V/2A N-Channel Metal Oxide Semiconductor F.E.T.
IEEE Transactions On Electron Devices, vol. ED-27, No. 2, Feb. 1980, S.C. Sun et al., "Modeling Of The On-Resistance Of LDMOS, VDMOS, and VMOS Power Transistors", pp. 356-367.
International Electron Devices Meeting--Tech. Digest, Dec. 8-10, 1980, Washington, D.C., pp. 91-94, J. Mena, et al., "High Frequency Performances of VDMOS Power Transistors".
Solid State Electronics, vol. 27, No. 5, pp. 419-432, 1984, P. McGregor, et al, "Small-Signal High-Frequency Performance Of Power MOS Transistors".
IEEE Transactions on Electron Devices, vol. ED-31, No. 1 Jan. 1984, pp. 109-113, Jose G. Mena, et al., "Breakdown Voltage Design Considerations in VDMOS Structures".
Solid State Electronics, vol. 29, No. 6, pp. 647-656, 1986, Jose G. Mena, et al., "High-Voltage Multiple-Resistivity Drift-Region LDMOS".
Solid State Electronics, 1977, vol. 29, pp. 875-878, Surinder Krishna, "Second Breakdown in High Voltage MOS Transistors".
Electronic Design, For Engineers and Engineering Managers--Worldwide, pp. 8276-8282, "HEXFET, A New Power Technology Cuts On-Resistance, Boosts Ratings".
Laid Open Patent Specification No. 85073/80, Laid Open Date: Jun. 26, 1980, Patent No. 75/162,677, Kanushiki Kaisha Hitachi Seisakusho, "Methods For Manufacturing Insulated Gate Type Field Effect Transistors".

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

High density MOS technology power device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High density MOS technology power device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High density MOS technology power device will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-995252

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.