High density metal insulator metal capacitors

Details High density metal insulator metal capacitors High density metal insulator metal capacitors

2001-05-22

2002-10-01

Reichard, Dean A. (Department: 2831)

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

C361S311000, C361S306100, C361S321600, C257S295000, C257S303000

Reexamination Certificate

active

06459562

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to capacitors in microelectronic devices and, more particularly, to thin-film metal insulator metal capacitors with dielectric material layers.
BACKGROUND OF THE INVENTION
Formation of predictable, reliable capacitors is desirable for several reasons. For example, mixed signal, radio frequency, and other circuits or devices may desirably include integrated capacitors with predictable and reliable electrical characteristics. In particular, these devices include capacitors with low voltage coefficients (the change of capacitance with voltage over an operating range), good capacitor matching, and relatively predictable capacitor values. In addition, if capacitors form part of an integrated circuit, it may be desirable to minimize additional processes or changes to processes required to form the capacitor. Accordingly, it is often desirable to form such capacitors using substantially standard semiconductor process flows such as CMOS, bipolar, and BiCMOS processes.
Capacitors for microelectronic devices may be formed in a variety of configurations. Often, such capacitors include two substantially parallel layers of conductive material separated by an insulating layer. Conductive materials typically include doped silicon substrate, polysilicon, or metal and insulating materials typically include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, tantalum oxide, aluminum oxide, barium strontium titanate, or other insulating materials.
The thin-film capacitor is generally formed by depositing, patterning, and etching various layers on a substrate. Typically, a first parallel layer of conductive material (a base plate) is formed by depositing the conductive material over the surface of the substrate, wherein the substrate may be a semiconductor wafer with several layers of conducting, insulating, semiconducting and semi-insulating layers thereon. Alternatively, the conductive material may be formed by doping the semiconductor substrate with substantially conductive material.
If the base plate is formed by depositing conductive material on the wafer surface, the material may be patterned with photoresist and etched using an appropriate wet or dry etch process. Similarly, and regardless of how the base plate was formed, the insulating layer may be formed by depositing insulating material over the surface of the wafer, patterning the insulating material, and etching the insulating material leaving at least some insulating material over at least a portion of the conducting layer. A second conducting layer (top plate of the capacitor) may be formed over the insulating layer in a like manner.
Typical capacitor materials and configurations of top and base capacitor plates generally include: a polysilicon top plate and a doped substrate base plate, a polysilicon top plate and a polysilicon base plate, metal top plate and a polysilicon base plate, or metal top plate and a metal base plate. Of these various capacitor configurations, such metal insulator metal (MIM) capacitors may be particularly advantageous because, among other reasons, they allow for increased distance from the substrate to the bottom plate, and they generally have lower voltage coefficients due to reduced voltage induced depletion effects at the metal to dielectric interface.
In an effort to reduce device and circuit costs, it is generally preferred to reduce the size of the devices and circuits and their corresponding capacitors. Capacitor size, for a given capacitance, may be reduced by increasing the capacitor's capacitance density. The increase in capacitance density can be achieved by using insulating layers with higher dielectric constant, by reducing the thickness of the insulating layer, or any combination thereof. However, as capacitance density increases, likewise, the voltage coefficient tends to increase as well. Currently, the industry standard for MIM capacitor density is about 1 to 1.5 fF/&mgr;m
2
.
Further, integration of MIM capacitors is typically done in upper metallization levels. Such integration places a limit on the deposition temperature to 400° C. or less because of the instability of the materials commonly used (e.g., aluminum, low-k dielectrics, and the like). However, dielectrics formed at such temperatures may have pinhole defects and charge traps, thereby resulting in dielectrics with higher leakage currents than dielectrics deposited at higher temperatures.
Still further, a preferred distance between conducting layers for a given dielectric material is often governed by voltage breakdown design parameters (leakage current). Breakdown voltage parameters are generally dependent upon, among other things, the minimum distance between conducting layers (corresponding to the thickness of the dielectric layer). This dielectric thickness is limited by the minimum allowable thickness to achieve manufacturability to target specifications of mean deposition thickness and uniformity. However, such low thicknesses may create increased leakage problems due to trapped charges and pinhole defects.
If either the insulating layer or the conducting layers, or a combination of the same have rough surfaces, the insulating layer thickness may have to be increased to compensate for the thinner regions of the layer such that the thinnest portion of the insulating layer provides adequate (e.g., sufficiently high) breakdown voltage characteristics. However, again, as low temperature oxide dielectric thickness gravitates towards thinner films, the leakage current generally increases.
For example, generally, nitride films tend to be leakier. In order to lower such leakage, composite stacks of typical films might be used. Unfortunately, however, film thickness becomes more difficult to control as the individual film thicknesses of the composite stack themselves become thinner. That is, using current industry standard equipment, film thickness variability and uniformity become more difficult to control as the films themselves become thinner.
Lastly, the capacitors formed as described above are often placed in a post anneal furnace (typically greater than 600° C.) for several hours in an oxygen rich or nitrogen rich environment in order to help fill up of the charge traps and improve film density. However, as mentioned above, MIM capacitors have restrictions of processing temperature to be less than 400° C. and, as such, high temperatures generally may not be used.
In order to overcome these high current leakage difficulties, alternative dielectric materials having higher dielectric constants have been substituted. Generally, these alternative materials include, for example, silicon nitride. However, such low temperature nitride films still tend to have higher leakage currents due to higher trapped charge densities
Thus, there exists a need for improved thin-film capacitors and for methods of forming the capacitors.
SUMMARY OF THE INVENTION
The present invention provides improved thin-film MIM capacitors and methods for forming the same. While the way in which the present invention addresses the various disadvantages of presently known capacitors will be addressed hereinbelow, in general, the invention provides a capacitor that is more reliable. In addition, the capacitor of the present invention may be formed with minimal additional processing steps.
In accordance with one embodiment of the present invention, a capacitor formed with alternating dielectric stacks is provided. For example, in accordance with one exemplary embodiment, a dielectric stack, such as a nitride stack is deposited in a plasma enhanced chemical vapor deposition process (PECVD) or a high density plasma (HDP) PECVD process. Next, reoxidation of the nitride stack is performed by immersion in an oxygen rich plasma in a HDP PECVD chamber, thereby forming an oxide rich stack on the top surface of the first nitride stack (an N-O configuration). In accordance with another aspect of the present invention, after adding the oxide stack, a second nitride stack may b

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