Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2006-05-23
2006-05-23
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S397000, C438S622000, C438S637000
Reexamination Certificate
active
07049204
ABSTRACT:
A metal-insulator-metal (MIM) capacitor is made according to a copper dual-damascene process. A first copper or copper alloy metal layer if formed on a substrate. A portion of the first metal layer is utilized as the lower plate of the MIM capacitor. An etch stop dielectric layer is used during etching of subsequent layers. A portion of an etch stop layer is not removed and is utilized as the insulator for the MIM capacitor. A second copper or copper alloy metal layer is later formed on the substrate. A portion of the second metal layer is utilized as the upper plate of the MIM capacitor.
REFERENCES:
patent: 5162258 (1992-11-01), Lemnios et al.
patent: 5792704 (1998-08-01), Jun et al.
patent: 5972192 (1999-10-01), Dubin et al.
patent: 5990015 (1999-11-01), Lin et al.
patent: 6048762 (2000-04-01), Hsia et al.
patent: 6081021 (2000-06-01), Gambino et al.
patent: 6184551 (2001-02-01), Lee et al.
patent: 6225207 (2001-05-01), Parikh
patent: 6297162 (2001-10-01), Jang et al.
patent: 6320244 (2001-11-01), Alers et al.
patent: 6329234 (2001-12-01), Ma et al.
patent: 6346454 (2002-02-01), Sung et al.
patent: 6399495 (2002-06-01), Tseng et al.
patent: 6472124 (2002-10-01), Chung
patent: 6475911 (2002-11-01), Lane
patent: 6479344 (2002-11-01), Huang et al.
patent: 6531372 (2003-03-01), Lee et al.
patent: 6569746 (2003-05-01), Lee et al.
patent: 6635523 (2003-10-01), Uchiyama et al.
patent: 6656788 (2003-12-01), Park et al.
patent: 6670256 (2003-12-01), Yang et al.
patent: 6759703 (2004-07-01), Matsuhashi
patent: 6921689 (2005-07-01), Matsuhashi
patent: 2001/0002722 (2001-06-01), Lee et al.
patent: 2002/0028552 (2002-03-01), Lee et al.
patent: 2002/0113297 (2002-08-01), Voldman et al.
patent: 1 073 101 (2001-01-01), None
patent: WO 00/46844 (2000-08-01), None
European Search Report for Appln No. EP 02 52 0004, Sep. 26, 2003 (date of completion of search) 3 pages.
Smith, “Application-Specific Integrated Circuits,” 8thEdition, May, 2000, Chapter 4, ProgrammableASICS, 4.1 The Antifuse, pp. 170-174.
Institute of Microelectriconics, “Deep Submicron—Advanced RFIC Integration,”IMEStrategic Focuses, htp://www.ime.org.sg/deep/deep/rfic.htm, Jun. 27, 2002, pp. 1-3.
Coleman W. David
Nguyen Khiem
LandOfFree
High density metal capacitor using via etch stopping layer... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High density metal capacitor using via etch stopping layer..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High density metal capacitor using via etch stopping layer... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3568803