High density memory module with in-line bus switches being enabl

Details High density memory module with in-line bus switches being enabl High density memory module with in-line bus switches being enabl

1998-05-12

2000-05-30

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710 14, 710 15, 710102, 710104, 710126, 711 2, 711 5, 711115, 711170, G06F 1300, G06F 1340, G06F 1200, G06F 1206

Patent

active

060702176

ABSTRACT:
Data line loading on high density modules with multiple DRAMs is minimized permitting the maximum memory density of systems of otherwise limited density to be increased without an ensuing performance degradation due to data line capacitive loading. First the single or dual in-line memory module (SIMM or DIMM) includes in-line bus switches. The bus switches are between the SIMM or DIMM module tabs (system) and random access memory devices (RAM) and are either in a high impedance (off) or active state depending on the READ/WRITE state of the RAM. When in the high impedance state, the effective loading of the module is that of the bit switch device. The logic for determining the READ/WRITE state may be embedded in an application specific integrated circuit (ASIC) that monitors bus activity and controls activation of the bus switches, be provided by a memory controller or, generated by the RAM itself. The bus switches are active when the RAM is performing a read or a write and inactive otherwise. The RAM is Fast Page Mode (FPM) and Extended Data Output (EDO) or Synchronous DRAM (SDRAM).

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