High density memory array system

Details High density memory array system High density memory array system

2006-06-02

2008-11-25

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Floating gate

C365S185050, C365S185260

Reexamination Certificate

active

07457154

ABSTRACT:
A memory system comprising a memory array having a plurality of memory units, a column decoder, a row decoder, a selecting/driving circuit and a sensing circuit is disclosed. Each memory unit comprises a gate electrode coupled to a word lines, a source region coupled to a source line or a first bit line, a drain region coupled to a drain line or a second bit line, a first spacer between the source region and the gate electrode and a second spacer between the drain region and the gate electrode. When a first-bit program operation is performed on the memory unit, a switch-on signal is applied to the gate, a programming signal is applied to the source region and the drain region is switched to ground. As the memory unit is activated, the carriers are injected and stored in a first spacer, thus represents a first bit in the memory unit.

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