High-density logic techniques with reduced-stack multi-gate...

Details High-density logic techniques with reduced-stack multi-gate... High-density logic techniques with reduced-stack multi-gate...

2008-04-14

2011-10-04

Ismail, Shawki (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S112000, C326S119000

Reexamination Certificate

active

08030971

ABSTRACT:
Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.

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