High density integrated semiconductor memory and method for prod

Details High density integrated semiconductor memory and method for prod High density integrated semiconductor memory and method for prod

1998-07-06

2000-12-05

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257315, 257319, 257623, H01L 29788

Patent

active

061570605

ABSTRACT:
The high density integrated semiconductor memory has an EPROM cell in the form of a pillar. The cell has a floating gate and a control gate. The EPROM cell is dimensioned so thin that it is fully depleted. The control gate of the preferred split gate flash EPROM cell or of the dual gate flash EPROM cell is composed of p.sup.+ -doped semiconductor material, so that the fully depleted cylinders exhibit superior lower threshold behavior.

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"A 3-D Sidewall Flash EPROM Cell and Memory Array" (Pein et al.), IEEE Electron Device Letters, vol. 14, No. 8, Aug. 1993, pp. 415-417.

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