High density integrated circuit packaging with chip stacking and

Details High density integrated circuit packaging with chip stacking and High density integrated circuit packaging with chip stacking and

1995-12-27

1999-12-14

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257686, 257741, 257746, 257777, H01L 2348, H01L 2302

Patent

active

060021772

ABSTRACT:
Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which may be stabilized by transient liquid phase (TLP) processes and preferably with or during metallization of conductive pads, possibly including connector patterns on both sides of at least some of the chips in the stack. At least some of the chips in the stack then have electrical and mechanical connections made therebetween, preferably with electroplated solder preforms consistent with TLP processes. The connections may be contained by a layer of resilient material surrounding the connections and which may be formed in-situ. High density circuit packages thus obtained may be mounted on a carrier by surface mount techniques or separable connectors such as a plug and socket arrangement. The carrier may be of the same material as the chip stacks to match coefficients of thermal expansion. High-density circuit packages may also be in the form of removable memory modules in generally planar or prism shaped form similar to a pen or as a thermal conduction module.

REFERENCES:
patent: 4394712 (1983-07-01), Anthony
patent: 4437109 (1984-03-01), Anthony et al.
patent: 4499655 (1985-02-01), Anthony
patent: 4754316 (1988-06-01), Reid
patent: 4841355 (1989-06-01), Parks
patent: 4939568 (1990-07-01), Kato et al.
patent: 4984358 (1991-01-01), Nelson
patent: 4991000 (1991-02-01), Bone et al.
patent: 5032896 (1991-07-01), Little et al.
patent: 5191405 (1993-03-01), Tomita et al.
patent: 5202754 (1993-04-01), Bertin et al.
patent: 5229647 (1993-07-01), Gnadinger
patent: 5270261 (1993-12-01), Bertin et al.
patent: 5399898 (1995-03-01), Rostoker
patent: 5404044 (1995-04-01), Booth et al.
patent: 5408123 (1995-04-01), Murai
patent: 5455445 (1995-10-01), Kurtz et al.
patent: 5510655 (1996-04-01), Tanielian
patent: 5528080 (1996-06-01), Goldstein
patent: 5530288 (1996-06-01), Stone
patent: 5552633 (1996-09-01), Sharma
patent: 5608264 (1997-03-01), Gaul
patent: 5637925 (1997-06-01), Ludden et al.
patent: 5859470 (1999-01-01), Ellerson et al.
"Cost and Pin Counts Rise in Shift to SMT"; PTS 941103617; Electronic Buyers' News; Feb. 21, 1994; p. 24; Bill Arnold.
"Good die, 3-D highland confab"; PTS 941103458; Electronic Engineering Times; Feb. 21, 1994, p. 77, Terry Costlow.

Affiliated with

Also associated with

Rating

High density integrated circuit packaging with chip stacking and does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High density integrated circuit packaging with chip stacking and, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High density integrated circuit packaging with chip stacking and will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-866225