High density integrated circuit device with MOS transistor and s

Details High density integrated circuit device with MOS transistor and s High density integrated circuit device with MOS transistor and s

1982-09-16

1985-09-03

James, Andrew J.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 68, 365174, 365 51, H01L 2994, H01L 2198

Patent

active

045395802

ABSTRACT:
A semiconductor device includes a dynamic memory area formed in a semiconductor substrate and set in an inequilibrium potential state, and a plurality of MOS transistors which emit minority carriers or more than a predetermined number into said semiconductor substrate during operation in a saturation region. Each of the MOS transistors is so arranged that a prolonged line extending in a direction from the source region to the drain region may cross the dynamic memory area.

REFERENCES:
patent: 4163245 (1979-07-01), Kinoshita
Jun-ichi Matsunaga et al., "Design Limitations Due to Substrate Currents and Secondary Impact Ionization Electrons in NMOS LSI's Proceedings of 11th Conference (1979 International) on Solid State Devices, Tokyo, 1979 Japanese Journal of Applied Physics, vol. 19, (1980), Supplement 19-1, pp. 93-97.

Affiliated with

Also associated with

Rating

High density integrated circuit device with MOS transistor and s does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High density integrated circuit device with MOS transistor and s, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High density integrated circuit device with MOS transistor and s will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-616448