High density input output

Details High density input output High density input output

2001-11-27

2003-12-30

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C438S460000, C438S462000

Reexamination Certificate

active

06671865

ABSTRACT:

FIELD
This invention relates to the field of integrated circuits. More particularly, the invention relates to a standardized and selectively configurable high density input/output array and flexible placement of input/output devices within the array.
BACKGROUND
Integrated circuit packages, such as application specific integrated circuit (ASIC) flip chips, typically include an array of electrical contacts for providing electrical input/output (IO) connection between the integrated circuit and a package substrate. Generally, the array of IO contacts provides direct connection between the integrated circuit and the package substrate without the use of wire bonds. Typically, the IO contacts are bumps of solder deposited on the integrated circuit in a particular pattern.
Within the integrated circuit there are IO devices, also referred to as IO cells, associated with each of the IO signals. In traditional designs, the IO devices are placed only along the periphery of the integrated circuit, and their associated contacts are located in an array around the integrated circuit. Metal traces within a redistribution metal layer are typically used to connect the IO devices to the IO contacts.
Placing the IO devices only along the periphery of the integrated circuit has several disadvantages. For circuits having a large number of IO devices, restricting the IO devices to only the periphery results in unnecessarily large integrated circuit sizes. As integrated circuit sizes increase to accommodate more and more IO devices, the length of the redistribution traces between the IO devices and the contacts typically must also increase, which degrades the performance of the integrated circuit. Placing the IO devices only along the periphery also results in long net connections to the core logic of the integrated circuit, which also degrades performance. Further, for a fixed integrated circuit size, restricting the IO devices to only the periphery limits the attainable IO density.
However, placing the IO devices along the periphery of the integrated circuit has typically been a preferred practice, because it tends to make the IO array more standardized, and thus tends to reduce production and packaging costs. In other words, developing and implementing customized IO arrays for every different integrated circuit design has been avoided in the past as being a prohibitively expensive and time consuming solution, the implementation of which tends to be worse than the problems which it is intended to resolve.
What is needed, therefore, is a placement pattern for IO devices and contacts on an integrated circuit which tends to alleviate the problems described above.
SUMMARY
The above and other needs are met by an input/output array having concentric rings of input/output tiles. The peripheral input/output tiles are adjacently arranged along the periphery of the integrated circuit to form a peripheral ring. Each of the peripheral input/output tiles is associated with a corresponding peripheral input/output device group which includes x
1
number of input/output devices. Each peripheral input/output tile includes x
1
number of signal contacts for coupling signals to corresponding ones of the x
1
number of input/output devices, y
1
number of input/output driver voltage contacts for coupling a source voltage to drivers of the x
1
number of input/output devices, and z
2
number of ground contacts.
The array also includes interior input/output tiles. The interior input/output tiles are adjacently arranged within the interior of the integrated circuit to form n number of substantially concentric interior rings, where n is greater than or equal to one. The n number of interior rings are substantially concentric with the peripheral ring. Each of the interior input/output tiles is associated with a corresponding interior input/output device group which includes x
2
number of input/output devices. Each interior input/output tile includes x
2
number of signal contacts for coupling signals to corresponding ones of the x
2
number of input/output devices, y
2
number of input/output driver voltage contacts for coupling a source voltage to drivers of the x
2
number of input/output devices, and z
2
number of ground contacts.
In this manner there is formed one or more standardized configurable input/output tiles for forming a selectively configurable input/output array for a variety of differently configured integrated circuits, where a plurality of the standardized configurable input/output tiles are selectively combinable into the input/output array in a fashion that is selectively configurable for the variety of differently configured integrated circuits. Thus, the standardized configurable input/output tiles can be configured in different ways to adapt to different integrated circuit designs, while maintaining their standardized nature, which tends to keep design costs, material costs, and inventory costs low. Therefore, a balance between standardization and configurability is struck.
In preferred embodiments of the invention, the signal contacts, input/output driver voltage contacts, and ground contacts of each peripheral input/output tile, and the corresponding peripheral input/output device group are aligned substantially perpendicular to an outer edge of the integrated circuit, nominally the nearest outer such outer edge. Also, in some preferred embodiments, the signal contacts, input/output driver voltage contacts, and ground contacts of each interior input/output tile, and the corresponding interior input/output device group are aligned substantially perpendicular to the outer edge of the integrated circuit.
Some preferred embodiments of the invention include n number of filler input/output tiles. At least one of the n number of filler input/output tiles is disposed between the peripheral ring and an outermost of the n number of interior rings. At least n−1 of the n number of filler input/output tiles are disposed between the n number of interior rings. Each of the filler input/output tiles includes one or more core voltage contacts for supplying power to circuit devices on the integrated circuit other than input/output devices, and one or more ground contacts.
Some preferred embodiments of the invention include a center input/output tile disposed within an innermost of the n number of interior rings. The center input/output tile includes one or more core voltage contacts for supplying power to circuit devices on the integrated circuit other than input/output devices, one or more input/output driver voltage contacts for coupling a source voltage to drivers of input/output devices, and one or more ground contacts.


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U.S. patent application entitled “Wire Bond Package with Core Ring Formed Over I/O Cells” filed on Feb. 20, 2002 (pending) US Ser. No. 10/082,027 First Named Inventor: Radoslav Ratchkov.

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