Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2000-07-13
2001-05-15
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S189110
Reexamination Certificate
active
06233198
ABSTRACT:
This application claims priority from Korean Patent Application No. 1999-28257, filed on Jul. 13, 1999, the contents of which are incorporated herein by reference in its entirety.
FIELD OF THE INVENTION
The present invention is related to semiconductor memory devices and, more particularly, to a NOR-type flash memory device with a row decoding structure that occupies a smaller area in a semiconductor integrated circuit die than conventional decoding structures.
BACKGROUND OF THE INVENTION
A memory cell unit of electrically erasable and programmable NOR-type flash memory devices has source and drain electrodes formed in a p-type semiconductor substrate, a floating gate electrode formed over a channel region between the source and drain electrodes with an insulator interposed therebetween, and a control gate electrode formed over the floating gate with another insulator interposed therebetween. The control gate electrode is connected to a word line.
The memory cell unit is programmed under a bias condition. The bias condition typically involves a ground voltage (e.g., 0V) applied to the memory cell's source electrode and substrate, a high voltage (e.g., +10V) applied to its control gate electrode, and a positive voltage (e.g., +5V to +6V) suitable for generating hot electrons applied to its drain electrode. The bias condition results in a sufficient amount of negative charges being accumulated in the floating gate electrode to thereby create a (−) potential in the floating gate electrode. The (−) potential forces the threshold voltage of the programmed cell to be increased during a read operation.
During the read operation where a voltage of about +5V is applied to the control gate electrode and a ground voltage is applied to the source electrode, the drain-source path of the programmed cell unit is nonconductive. At this time, the memory cell unit has an “OFF” state, and its threshold voltage is distributed between +6V to +7V.
The memory cell unit is erased by the Fowler-Nordheim (F-N) tunneling mechanism. The F-N tunneling mechanism functions as follows. A negative high voltage (e.g., −10V) applied to the control gate electrode and a positive voltage (e.g., +5V to +6V) suitable to induce the F-N tunneling is applied to the semiconductor substrate. The source and drain electrodes are maintained at a floating, state. The erase operation of such a bias condition is referred to as “Negative Bulk and Gate Erase” operation. The bias condition creates a strong electric field of 6 to 7 MV/cm between the control gate electrode and the semiconductor substrate. As a result, negative charges accumulated in the floating gate electrode are discharged in the source electrode through the insulator. The insulator typically has a thickness of about 100 angstrom. The discharge of negative charges lower the threshold voltage of the erased cell during the read operation.
During the read operation where a voltage of about +5V is applied to the control gate electrode and a ground voltage is applied to the source electrode, the drain-source path of the programmed cell unit is conductive. At this time, the memory cell unit has an “ON” state and its threshold voltage is between +1V to +3V.
As is well known in the art, the memory cell array of the NOR-type flash memory device is divided into a plurality of sectors. The bulk region of the each sector is electrically isolated. The memory cells integrated in each sector are simultaneously erased during an erase operation. A typical NOR-type flash memory device having a sector structure and a row decoder circuit are disclosed in entitled “
A
3.3
V
-
only
, 16
Mb Flash Memory with Row
-
Decoding Scheme
” IEEE International Solid State Circuits, vol. 2, pp. 42-43 (1996), which is hereby incorporated by reference. The structure of the flash memory device disclosed in the reference is illustrated in FIG.
1
. The capacity of the memory cell array
10
illustrated in
FIG. 1
is 16 Mb and the array is divided into 32 uniform sectors (or blocks), e.g., 12, 14, and 16, each having the capacity of 0.5 Mb (512 colums*1024 rows). The rows (i.e., word lines) and the columns (i.e., bit lines) of each sector are selected independently from each other. This architecture allows disturbance-free program/erase operations, resulting in high reliability.
FIG. 2
is a circuit diagram of a row decoder circuit
20
disclosed in the aforementioned reference. The row decoder circuit
20
includes a row global decoder
22
, a row partial decoder
24
, a row local decoder
26
and a block decoder
28
. Various word line voltages depending on read/program/erase operations are transferred to individual word line(s). The row local decoder
26
includes two transfer gates TG
1
and TG
2
arranged so as to correspond to the respective word lines. The transfer gate TG
1
comprises PMOS transistors and NMOS transistor N
1
similarly, the transfer gate TG
2
comprises PMOS-transistors P
2
and NMOS transistor N
2
. The word lines are coupled to corresponding outputs from the row partial decoder
24
through the row local decoder
26
in accordance with signals on the global word lines, e.g., word lines
30
and
32
, during the program/read operation. All of the word lines are connected to the output from the block decoder
28
through the row local decoder
26
.
A problem arises when the row decoder circuit
20
is used in a high-density flash memory device. The structure of the row decoder circuit
26
is inappropriate to the flash memory device when the density of the memory device is increased. Four MOS transistors, e.g., P
1
, N
1
, P
2
and N
2
, are required for each word line (or a local word line) to select and drive the selected word line. Furthermore, the transistors coupled to each local word line load the word line during read/program/erase operations, resulting in operating speed loss.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the problems associated with prior art memory devices.
It is another object of the present invention to provide a row decoder circuit for a flash memory device that can occupy a smaller area in an integrated circuit die than a conventional decoder circuit.
In order to attain the above objects, a nonvolatile semiconductor memory device having a hierarchical word line structure is provided. The semiconductor memory device comprises a sector having a plurality of memory cells coupled to corresponding local word lines. A global word line selecting circuit having a first global decoder and a second global decoder, the first global decoder generating an odd-numbered global word line and the second global decoder generating an even-numbered global word lines. A plurality of first local decoders is coupled to the odd-numbered global decoder. Each first local decoder drives one of the plurality of local word lines with a word line voltage responsive to the odd-numbered global word line. A plurality of second local decoders is coupled to the even-numbered global decoder. Each second local decoder drives another of the plurality of local word lines with the word line voltage responsive to the even-numbered global word line is selected.
Each first local decoder includes a plurality of first drivers coupled to a first subset of the plurality of local word lines first each driver including a first pull-up transistor and a first pull-down transistor. Each second local decoder includes a plurality of second drivers coupled to a second subset of the plurality of local word lines, each second driver including a second pull-up transistor and a second pull-down transistor.
The first pull-up transistor connects a local word line from the first subset to a row partial decoder responsive to the even-numbered global word line. The first pull-down transistor connects the local word line from the first subset to a block decoder responsive to the even-numbered global word line. The second pull-up transistor connects a local word line from the second subset to the r
Marger & Johnson & McCollom, P.C.
Phan Trong
Samsung Electronics Co,. Ltd.
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