High density flash memory cell

Details High density flash memory cell High density flash memory cell

1999-05-06

2001-09-25

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S264000

Reexamination Certificate

active

06294812

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 88105507, filed Apr. 7, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a flash memory cell, and more particularly, to a high density flash memory cell with a self-aligned tunneling window.
2. Description of the Related Art
Recently, the wide application of memories with a high density in many fields have evoked a great attention. One of the reasons is that the memory cell and the fabrication cost can be greatly reduced. However, using the conventional local oxidation isolation (LOCOS) technique restricts the development of the fabrication technique in the deep sub-micron process.
The development of shallow trench isolation has resolved the restriction of the local oxidation isolation technique. A memory with a high density can be fabricated with a further shrunk dimension.
In a conventional flash memory cell, a tunneling oxide layer is formed between a controlling gate and a floating gate instead of being formed on the surface of the source/drain region. Therefore, the electron is tunneled in and out of the floating gate by way of a semiconductor channel. The way of electron tunneling comprises a Fowler Nordheim (FN) tunneling, a channel hot electron injection (CHEI), a band-to-band tunneling induced hot carrier injection (BBHC), or other mechanism.
No matter which way of electron tunneling is employed, an operation voltage has to reach a certain value during a reading, programming, or erasing process. Thus causes a restriction of layout.
SUMMARY OF THE INVENTION
Accordingly, the invention provides a flash memory cell. The flash memory cell comprises a self-aligned source and drain regions formed to advantage a fabrication process with further shrinking linewidth. That is, by the self-aligned fabrication process, the source and drain regions can be formed with a small dimension. Moreover, by a self-aligned forming step, a tunneling layer is formed directly on the source and drain region. As consequence, the tunneling layer can be formed with a length ranged between 500 Å to 2000 Å. Over the channel region between the drain region and the source region, a gate oxide layer is formed with a length of about 0.1 to 0.5 &mgr;m. With such a small tunneling window of the self-aligned source/drain region, the tunneling effect is thus enhanced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5429960 (1995-07-01), Hong
patent: 5457061 (1995-10-01), Hong et al.
patent: 5851881 (1998-12-01), Lin et al.
patent: 5918125 (1999-06-01), Guo et al.
patent: 5972752 (1999-10-01), Hong
patent: 5978264 (1999-11-01), Onakado et al.

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