Fishing – trapping – and vermin destroying
Patent
1991-04-17
1992-09-01
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 44, 437 49, 437195, H01L 2144
Patent
active
051438607
ABSTRACT:
An EPROM memory having sidewall floating gates (30) is disclosed. Sidewall floating gates (30) are formed on sidewalls (28) of field insulators (24). Spaced apart bit lines (22), which serve as memory cell sources and drains, are formed. The field insulators (24) overlie the bit lines (22), and sidewall floating gates are formed on the sidewalls (28) of the field insulators (24). In one embodiment, a second set of bit lines (36) is formed between the sidewall floating gates (30), and each memory cell contains one sidewall floating gate (30). In another embodiment, each memory cell contains two sidewall floating gate (30), and the memory cell may be programmed to store from two to four distinct information states.
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Mitchell Allan T.
Riemenschneider Bert R.
Tigilaar Howard L.
Bassuk Lawrence J.
Brady III W. James
Chaudhari C.
Donaldson Richard L.
Hearn Brian E.
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