High density electrically erasable floating gate dual-injection

Details High density electrically erasable floating gate dual-injection High density electrically erasable floating gate dual-injection

1980-06-02

1983-05-17

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Erase

365189, G11C 1300

Patent

active

043843492

ABSTRACT:
An improved electrically erasable semiconductor memory device of the N-channel, MOS, double level poly, programmable, read only memory or EPROM type is provided; the device is a very dense array of cells which may be electrically erased and programmed by dual injection into floating gates which are interposed between the channels and control gates. The electrical erasure or programming of the cells is accomplished by applying selected voltages to the source, drain, control gate and substrate to produce injection of electrons or holes. The avalanche breakdown voltage is increased by a high voltage on the row lines; the selected row line is grounded to allow erasure of a single bit or byte. The very dense array results from a simplified structure and manufacturing process which may be generally the same as prior N-channel floating gate EPROM technology.

REFERENCES:
patent: 3875567 (1975-04-01), Yamazaki et al.
patent: 4308596 (1981-12-01), Takai et al.

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