High density EEPROM cell with tunnel oxide stripe

Details High density EEPROM cell with tunnel oxide stripe High density EEPROM cell with tunnel oxide stripe

1992-06-01

1994-03-08

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

257321, 257315, 257346, G11C 1134

Patent

active

052933318

ABSTRACT:
An electrically erasable programmable read only memory (EEPROM) cell and fabrication process includes first field oxide regions (FOX1) formed in a P-well in an N-substrate to define a p-type device region. Buried N+ bit lines formed in the substrate adjacent to FOX1 regions define a p-channel region. Second field oxide (FOX2) regions overlying the N+ bit lines. A gate oxide layer is formed on the substrate between the FOX2 regions. A tunnel stripe is then defined in the gate oxide; the gate oxide is etched from the stripe; and a tunnel oxide stripe is grown in the etched stripe. The tunnel oxide stripe extends across a plurality of EEPROM cells sharing common bit lines. A layer of polysilicon is formed extending over the tunnel oxide stripe, thus defining a floating gate for the cell. The intersection of the tunnel oxide stripe and the floating gate defines the tunneling region for each cell. A layer of oxide
itride/oxide (ONO) composite is formed over the floating gate. A second polysilicon layer and an overlying tungsten silicide are then formed over the ONO to define the control gate.

REFERENCES:
patent: 4947222 (1990-08-01), Gill et al.
patent: 4979005 (1990-12-01), Mitchell
patent: 5051796 (1991-09-01), Gill
patent: 5057886 (1991-10-01), Riemenschneider et al.
patent: 5156990 (1992-10-01), Mitchell

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