Static information storage and retrieval – Floating gate – Particular biasing
Patent
1992-06-01
1995-01-03
LaRoche, Eugene R.
Static information storage and retrieval
Floating gate
Particular biasing
257321, 257315, 257346, 437 52, 437 43, H01L 2968
Patent
active
053792530
ABSTRACT:
A high density, electrically-erasable programmable read-only memory (EEPROM) cell is fabricated and used. Forming field oxide regions (FOX1) in a P-well defines a p-type active device region. Forming N+ buried bit lines in the substrate adjacent to the FOX1 regions defines a P-channel region. Forming additional field oxide regions (FOX2) adjacent to the FOX1 regions covers the bit lines. A gate oxide layer is formed between the FOX2 regions, upon which a tunnel oxide window is defined. A polysilicon layer covers the gate oxide and forms the floating gate for the cell. An oxide
itride/oxide (ONO) layer covers the floating gate. A polysilicon/tungsten silicide layer covers the ONO defining the control gate for the cell. The cell is programmed by simultaneously holding the control gate (word line) at a high programming voltage, the bit lines at a low supply voltage, and the P-well at ground; while the word lines of adjacent cells having the same bit lines are grounded, and while the bit lines of adjacent cells having the same word line are held at the programming voltage. The cell is erased by simultaneously holding the control gate (word line) at a low supply voltage, the bit lines at the programming voltage, and the P-well at the programming voltage; while the word lines of adjacent cells having the same bit lines and the bit lines of adjacent cells having the same word line are all held at the programming voltage.
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Boaz Eitan, R. Kazerounian and A. Bergemont, "Alternate Metal Virtual Ground (AMG)--A New Scaling Concept for Very High-Density EPROM's", IEEE Electron Device Letters, vol. 12, No. 8, Aug. 1991, New York, U.S., pp. 450-451.
LaRoche Eugene R.
Le Vu
National Semiconductor Corporation
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