High-density DRAM structure on soi

Details High-density DRAM structure on soi High-density DRAM structure on soi

1992-06-17

1996-06-18

Meier, Stephen D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257300, 257301, H01L 27108, H01L 2976, H01L 2994, H01L 31119

Patent

active

055280625

ABSTRACT:
A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bit array shown schematically in FIG. 1b. Trench storage capacitors and vertical FET transistors are arranged in pairs with a common vertical gate and a common substrate, allowing both bit and substrate contacts to be shared by adjacent cells.

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