Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
1998-02-20
2002-01-01
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S124000, C438S612000, C438S615000, C438S616000
Reexamination Certificate
active
06335225
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention: The present invention relates to an apparatus and method for attaching a semiconductor die to a lead frame or other type of connector. More particularly, the present invention relates to relocating electric contact points of a semiconductor die to the periphery of the semiconductor die through a plurality of conductive traces. The leads of the lead frame extend over the conductive traces proximate the semiconductor periphery and directly attach to and make electrical contact with the conductive traces in a variety of arrangements or configurations. Alternately, a connector may be used to contact a portion of the end of a conductive trace located at the periphery of a semiconductor die.
State of the Art: Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are goals of the computer industry. Greater integrated circuit density is primarily limited by the space or “real estate” available for mounting a semiconductor die on a substrate such as a printed circuit board. Conventional lead frame design inherently limits package density for a given semiconductor die size because the die-attach paddle of the lead frame must be larger than the die to which it is bonded. The larger the semiconductor die, the less space that remains around the periphery of the die-bonding pad for wire bonding. Furthermore, the wire bonding pads on the standard lead frame provide anchorage for the leads when the leads and the semiconductor die are encapsulated in plastic. Therefore, as the die size is increased in relation to a given package size, there is a corresponding reduction in the space along the sides of the package for the encapsulating plastic which joins the top and bottom of the plastic body at the mold part line and anchors the leads. Thus, as the leads and encapsulant are subjected to the normal stresses of subsequent forming and assembly operations, the encapsulating plastic may crack, compromising package integrity and substantially increasing the probability of premature device failure.
Also, since lead frames are designed for use with a semiconductor die having a specific pattern of bond pads located on the active surface thereof, it is desirable to have the flexibility of changing the bond pad locations of a die so that an existing lead frame design may be used with differing types of die.
For example, one method of chip attachment which reduces the die size is a so-called “lead-over-chip” (“LOC”) arrangement. Conventional LOC devices have a plurality of leads which is disposed on and attached to an active surface of a semiconductor die, thus the name lead-over-chip. A primary advantage of LOC is that the ratio between the size of the semiconductor die and the size of a package which encapsulates the semiconductor die is high. This advantage is achieved because the die-attach paddle is not required since the semiconductor die is instead attached to the leads.
U.S. Pat. No. 4,862,245 issued Aug. 29, 1989 to Pashby et al. (“the '245 patent”) illustrates a LOC arrangement on a semiconductor die (see FIG.
10
). The leads
16
are extended over a semiconductor die
10
toward a central or axial line of bond pads
14
wherein bond wires
12
make the electrical connection between the inner ends of leads
16
and the bond pads
14
. In wirebonding, the bond wires
12
are attached, one at a time, to each bond pad
14
on the semiconductor die
10
and extend to a corresponding lead or trace end
16
on a lead frame or printed circuit board (not shown). The bond wires
12
are generally attached through one of three industry-standard wirebonding techniques: ultrasonic bonding—using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bonding—using a combination of pressure and elevated temperature to form a weld; and thermosonic bonding—using a combination of pressure, elevated temperature, and ultrasonic vibration bursts. Film-type alpha barriers
18
are provided between the semiconductor die
10
and the leads
16
, and are adhered to both, thus eliminating the need for a separate die paddle or other die support aside from the leads
16
themselves. The configuration of the '245 patent assists in limiting the ingress of corrosive environmental contaminants to the active surface of the die, achieves a larger portion of the circuit path length encapsulated in the packaging material applied after wire bonding, and reduces electrical resistance caused by the bond wires
12
by placing the lead ends in closer proximity to the bond pads
14
(i.e. the longer the bond wire, the higher the resistance). Although this configuration offers certain advantages, it requires that bond wires
12
be individually attached between the bond pads
14
and the leads
16
. Bond wires have an inherent problem called bond wire sweep. When encapsulating a bare die assembly, the die assembly is generally placed in a mold with a molten encasing material being injected into the mold whereby the encasing material surrounds the die assembly and the material conforms to the mold. However, this process causes stresses on the bond wires. Since the molten encasing material is viscous, it tends to place directional forces on the bond wires as the encasing material is injected into the mold. These directional forces cause the bond wires to stretch which can, in turn, cause the bond wires to short with adjacent bond wires or bond pads or be pulled from a bond pad or lead to which the wires are bonded.
U.S. Pat. No. 5,252,853 issued Oct. 12, 1993 to Michii illustrates a LOC arrangement on the semiconductor die which does not use bond wires (see FIG.
11
). The leads
22
are extended over a semiconductor die
20
toward centrally located bond pads
24
(shown in shadow). The leads
22
extend to a position over their respective bond pads
24
wherein the leads
22
are bonded directly to their bond pads
24
with TAB attachment. Although this direct bonding of the lead to the bond pad eliminates the need for wirebonding, it still requires lengthy leads to make electrical contact between the bonds pads and the lead frame. Film-type alpha barriers
26
are also provided between the semiconductor die
20
and the leads
22
.
Therefore, it would be advantageous to develop a technique and a device for increasing integrated circuit density by reducing lead width and reducing bond pad size, using non-complex lead frame configurations, and eliminating bond wires, while using commercially-available, widely-practiced semiconductor device fabrication techniques.
SUMMARY OF THE INVENTION
The present invention relates to an apparatus and method for attaching a semiconductor die to a lead frame or other type connector, such as a clip type. Electric contact points of the semiconductor die of the present invention are relocated to the periphery of a semiconductor die and are in electrical contact with a lead frame or connector. The semiconductor die may be in electrical contact with a lead frame through at least one lead which extends over and directly attaches to its respective electric contact point on the semiconductor die periphery, or through one lead which extends over and is attached to a die contact point with electrical contact being made to the electrical contact point of the die by means of a wire bond, or through one lead which extends adjacent the edge of a die with electrical contact being made to the electrical contact point of the die by means of a wire bond.
The apparatus is constructed by first forming a semiconductor die on a semiconductor wafer. A plurality of electric contact points, such as bond pads, is disposed on an active surface of the semiconductor die. A plurality of conductive traces is formed on the semiconductor die active surface to make a conductive route between each electric contact point and a position proximate to the semiconductor die periphery. A plurality of edge electric contact points may be formed on the periph
Micro)n Technology, Inc.
Rao Shriniras H.
TraskBritt
LandOfFree
High density direct connect LOC assembly does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High density direct connect LOC assembly, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High density direct connect LOC assembly will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2867478