High density buried bit line flash EEPROM memory cell with a sha

Details High density buried bit line flash EEPROM memory cell with a sha High density buried bit line flash EEPROM memory cell with a sha

1998-06-30

2000-10-24

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257314, H01L 29788

Patent

active

061371327

ABSTRACT:
The structure of flash EEPROM is formed on a composite substrate, wherein said composite substrate comprises: a pad oxide layer formed on a semiconductor substrate; an n-type doped dielectric layer is formed on the pad oxide layer. A nitride layer is formed on the n-type doped oxide layer. The composite substrate has a trench. An oxynitride layer which serves as coupling oxide layer is formed on surfaces of sidewalls and bottom of portion of the semiconductor substrate of the trench. The trench is filled with an n-type conductive doped polysilicon layer. The n-type conductive doped polysilicon layer serves as a floating gate of EEPROM. A conductive layer, a semiconductor substrate layer doped by using aforementioned n-type dopant containing oxide as a diffusion source, serves as buried bit lines being formed in the semiconductor substrate and abutting the pad oxide layer. An ONO layer is formed on the polysilicon layer and the nitride layer. Finally, another n+ conductive layer is formed on the ONO layer as word line.

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