High data throughput turbo product encoder

Details High data throughput turbo product encoder High data throughput turbo product encoder

2007-08-30

2011-11-22

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

08065585

ABSTRACT:
A source controller provides a block of n×a information bits as n separate rows each with a information bits. A row encoder has an input coupled to an output of the source controller and includes a plurality of accumulators arranged to process m of the information bits in one clock cycle to generate row forward error correction FEC bits. At least one column encoder has an input coupled to an output of the source controller and is arranged to generate column FEC bits in parallel with the row encoder. A multiplexer is coupled to outputs of the row and column encoders and is adapted to serially output an nthrow of information bits followed by the nthrow FEC bits for each of the n rows, followed by additional rows of FEC bits generated by the column encoder. The terms n, m, and a are integers greater than one. Where more than one column encoder is used, there are preferably m column encoders in parallel and each operating at one bit per clock cycle.

REFERENCES:
patent: 6581178 (2003-06-01), Kondo
patent: 6622277 (2003-09-01), Ramanujam et al.
patent: 7246294 (2007-07-01), Kauschke et al.
patent: 2003/0188248 (2003-10-01), Kauschke et al.

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